TDRSHAX1.v
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// VERSION:4.00 DATE:00/02/15 OPENCAD Verilog LIBRARY
`timescale 1ps / 1ps
`celldefine
`ifdef verifault
`suppress_faults
`enable_portfaults
`endif
module TDRSHAX1 ( N01, N02, H01, H02, H03 );
input H01;
input H02;
input H03;
output N01;
output N02;
reg notifier;
reg docheck1;
reg docheck2;
buf ( _H01, H01 );
buf ( _H02, H02 );
buf ( _H03, H03 );
udp_RSQ ( _G011, _H01, _H02, _H03, 1'b1, 1'b1, notifier );
udp_RSQB ( _G012, _H01, _H02, _H03, 1'b1, 1'b1, notifier );
buf ( N01, _G011 );
buf ( N02, _G012 );
buf #1 ( _G098, _G011 );
buf #1 ( _G099, _G012 );
`ifdef INCA
buf #1 ( _docheck1, docheck1 );
buf #1 ( _docheck2, docheck2 );
`else
`ifdef VCS
buf #1 ( _docheck1, docheck1 );
buf #1 ( _docheck2, docheck2 );
`else
buf ( _docheck1, docheck1 );
buf ( _docheck2, docheck2 );
`endif
`endif
initial //initialize data flags
begin
docheck1 = 0;
docheck2 = 0;
end
always @( _H01 or _H02 )
begin
docheck1 = ( _H01 !== _H02 );
if ( _H03 === 1'b0 )
docheck2 = ( ((_G098 !== _H01) || (_G099 !== _H02)) &&
(_H01 !== _H02) );
end
always @( posedge _H03 )
begin
docheck2 = ( ((_G098 !== _H01) || (_G099 !== _H02)) &&
(_H01 !== _H02) );
end
specify
specparam DMY_SPC=1;
$setup ( posedge H01, negedge H03 &&& _docheck1, DMY_SPC, notifier );
$setup ( negedge H01, negedge H03 &&& _docheck1, DMY_SPC, notifier );
$hold ( negedge H03, posedge H01 &&& _docheck1, DMY_SPC, notifier );
$hold ( negedge H03, negedge H01 &&& _docheck1, DMY_SPC, notifier );
$setup ( posedge H02, negedge H03 &&& _docheck1, DMY_SPC, notifier );
$setup ( negedge H02, negedge H03 &&& _docheck1, DMY_SPC, notifier );
$hold ( negedge H03, posedge H02 &&& _docheck1, DMY_SPC, notifier );
$hold ( negedge H03, negedge H02 &&& _docheck1, DMY_SPC, notifier );
$width ( posedge H03 &&& _docheck2, DMY_SPC, 0, notifier );
if ( H03 )
( H01 +=> N01 ) = ( DMY_SPC, DMY_SPC );
if ( H03 && !H02 )
( posedge H01 => ( N02 +: 1'b0 )) = ( 0:0:0, DMY_SPC );
if ( H03 && !H01 )
( posedge H02 => ( N01 +: 1'b0 )) = ( 0:0:0, DMY_SPC );
if ( H03 )
( H02 +=> N02 ) = ( DMY_SPC, DMY_SPC );
if ( H01 && !H02 )
( posedge H03 => ( N01 +: 1'b1 )) = ( DMY_SPC, 0:0:0 );
if ( !H01 && H02 )
( posedge H03 => ( N01 +: 1'b0 )) = ( 0:0:0, DMY_SPC );
if ( H01 && H02 )
( H03 => N01 ) = ( DMY_SPC, DMY_SPC );
if ( H01 && !H02 )
( posedge H03 => ( N02 +: 1'b0 )) = ( 0:0:0, DMY_SPC );
if ( !H01 && H02 )
( posedge H03 => ( N02 +: 1'b1 )) = ( DMY_SPC, 0:0:0 );
if ( H01 && H02 )
( H03 => N02 ) = ( DMY_SPC, DMY_SPC );
endspecify
endmodule
`ifdef verifault
`nosuppress_faults
`disable_portfaults
`endif
`endcelldefine