TDTBFNEX8.v
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// VERSION:4.00 DATE:00/02/15 OPENCAD Verilog LIBRARY
`timescale 1ps / 1ps
`celldefine
`ifdef verifault
`suppress_faults
`enable_portfaults
`endif
// generated by sldtoveri Version 1.3.4
// Wed Nov 8 15:59:06 1995
module TDTBFNEX8 ( N01 , H01 , H02 ) ;
input H01 ;
input H02 ;
output N01 ;
buf ( _H01 , H01 ) ;
buf ( _H02 , H02 ) ;
bufif1 ( _N01 , _H01 , _H02 ) ;
bufif1 ( N01 , _N01 , _H02 ) ;
specify
specparam DMY_SPC=1;
// path from H01 to N01
( H01 *> N01 ) = ( DMY_SPC,
DMY_SPC );
// path from H02 to N01
( H02 *> N01 ) = ( 0:0:0,
0:0:0,
DMY_SPC,
DMY_SPC,
DMY_SPC,
DMY_SPC );
endspecify
endmodule
`ifdef verifault
`nosuppress_faults
`disable_portfaults
`endif
`endcelldefine