TDXR3X1.v
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// VERSION:4.00 DATE:00/02/15 OPENCAD Verilog LIBRARY
`timescale 1ps / 1ps
`celldefine
`ifdef verifault
`suppress_faults
`enable_portfaults
`endif
module TDXR3X1 ( N01, H01, H02, H03 );
input H01;
input H02;
input H03;
output N01;
buf ( _H01, H01 );
buf ( _H02, H02 );
buf ( _H03, H03 );
xor ( N01, _H01, _H02, _H03 );
specify
specparam DMY_SPC=1;
if ( H01 )
( H01 *> N01 ) = ( DMY_SPC, DMY_SPC );
if ( !H01 )
( H01 *> N01 ) = ( DMY_SPC, DMY_SPC );
if ( H02 )
( H02 *> N01 ) = ( DMY_SPC, DMY_SPC );
if ( !H02 )
( H02 *> N01 ) = ( DMY_SPC, DMY_SPC );
if ( H03 )
( H03 *> N01 ) = ( DMY_SPC, DMY_SPC );
if ( !H03 )
( H03 *> N01 ) = ( DMY_SPC, DMY_SPC );
endspecify
endmodule
`ifdef verifault
`nosuppress_faults
`disable_portfaults
`endif
`endcelldefine