TBSMDFHQY0.v
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// VERSION:4.00 DATE:2001/05/14 OPENCAD Verilog LIBRARY
`timescale 1ps / 1ps
`celldefine
`ifdef verifault
`suppress_faults
`enable_portfaults
`endif
module TBSMDFHQY0 ( N01, H01, H02, H03, H04 );
input H01;
input H02;
input H03;
input H04;
output N01;
reg notifier;
reg docheck1;
reg docheck2;
reg docheck3;
reg docheck4;
reg docheck5;
buf ( _H01, H01 );
not ( _G001, _H01 );
buf ( _H02, H02 );
buf ( _H03, H03 );
not ( _G002, _H03 );
buf ( _H04, H04 );
not ( _G003, _H04 );
and ( _G010, _G001, _G002 );
and ( _G011, _G001, _G003 );
and ( _G012, _G002, _H04 );
nor ( _G013, _G010, _G011, _G012 );
buf ( N01, _G004 );
DESFQ ( _G004, _G013, _H02, 1'b1, 1'b1, notifier );
buf #1 ( _G099, _G004 );
`ifdef INCA
buf #1 ( _docheck1, docheck1 );
buf #1 ( _docheck2, docheck2 );
buf #1 ( _docheck3, docheck3 );
buf #1 ( _docheck4, docheck4 );
buf #1 ( _docheck5, docheck5 );
`else
`ifdef VCS
buf #1 ( _docheck1, docheck1 );
buf #1 ( _docheck2, docheck2 );
buf #1 ( _docheck3, docheck3 );
buf #1 ( _docheck4, docheck4 );
buf #1 ( _docheck5, docheck5 );
`else
buf ( _docheck1, docheck1 );
buf ( _docheck2, docheck2 );
buf ( _docheck3, docheck3 );
buf ( _docheck4, docheck4 );
buf ( _docheck5, docheck5 );
`endif
`endif
initial //initialize data flags
begin
docheck1 = 0;
docheck2 = 0;
docheck3 = 0;
docheck4 = 0;
docheck5 = 0;
end
always @( _H01 or _H03 or _H04 or _G013 )
begin
docheck1 = ( _H04 !== 1'b1 );
docheck2 = ( _H04 !== 1'b0 );
docheck3 = ( _H01 !== _H03 );
if ( _H02 === 1'b0 )
docheck4 = ( _G099 !== _G013 );
if ( _H02 === 1'b1 )
docheck5 = ( _G099 !== _G013 );
end
always @( posedge _H02 )
begin
docheck1 = ( _H04 !== 1'b1 );
docheck2 = ( _H04 !== 1'b0 );
docheck4 = ( _G099 !== _G013 );
docheck5 = 1;
end
always @( negedge _H02 )
begin
docheck4 = ( _G099 !== _G013 );
end
specify
specparam DMY_SPC=1;
$setup ( posedge H01, posedge H02 &&& _docheck1, DMY_SPC, notifier );
$setup ( negedge H01, posedge H02 &&& _docheck1, DMY_SPC, notifier );
$hold ( posedge H02, posedge H01 &&& _docheck1, DMY_SPC, notifier );
$hold ( posedge H02, negedge H01 &&& _docheck1, DMY_SPC, notifier );
$setup ( posedge H03, posedge H02 &&& _docheck2, DMY_SPC, notifier );
$setup ( negedge H03, posedge H02 &&& _docheck2, DMY_SPC, notifier );
$hold ( posedge H02, posedge H03 &&& _docheck2, DMY_SPC, notifier );
$hold ( posedge H02, negedge H03 &&& _docheck2, DMY_SPC, notifier );
$setup ( posedge H04, posedge H02 &&& _docheck3, DMY_SPC, notifier );
$setup ( negedge H04, posedge H02 &&& _docheck3, DMY_SPC, notifier );
$hold ( posedge H02, posedge H04 &&& _docheck3, DMY_SPC, notifier );
$hold ( posedge H02, negedge H04 &&& _docheck3, DMY_SPC, notifier );
$width ( posedge H02 &&& _docheck4, DMY_SPC, 0, notifier );
$width ( negedge H02 &&& _docheck5, DMY_SPC, 0, notifier );
( posedge H02 => ( N01 +: 1'b1 )) = ( DMY_SPC, DMY_SPC );
endspecify
endmodule
`ifdef verifault
`nosuppress_faults
`disable_portfaults
`endif
`endcelldefine