TDSMDFHQYRBX1.v
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// VERSION:3.00 DATE:00/02/16 OPENCAD Verilog LIBRARY
`timescale 1ps / 1ps
`celldefine
`ifdef verifault
`suppress_faults
`enable_portfaults
`endif
module TDSMDFHQYRBX1 ( N01, H01, H02, H03, H04, H05 );
input H01,H02,H03,H04,H05;
output N01;
reg notifier;
buf ( _H01, H01 );
buf ( _H02, H02 );
buf ( _H03, H03 );
buf ( _H04, H04 );
buf ( _H05, H05 );
and ( _G001, _H01, _H03 );
udp_MUX ( _G002, _H05, _G001, _H04 );
DESFQ ( _G003, _G002, _H02, 1'b1, 1'b1, notifier );
buf ( N01, _G003 );
wire docheck1 = ( (_H03!==1'b0) && (_H05!==1'b1) );
wire docheck2 = ( (_H01!==1'b0) && (_H05!==1'b1) );
wire docheck3 = ( _H05!==1'b0 );
wire docheck4 = ( (_H03!==1'b0) && (_H01!==_H04) );
specify
specparam DMY_SPC = 1;
$setup( posedge H01, posedge H02 &&& docheck1, DMY_SPC, notifier );
$setup( negedge H01, posedge H02 &&& docheck1, DMY_SPC, notifier );
$hold( posedge H02, posedge H01 &&& docheck1, DMY_SPC, notifier );
$hold( posedge H02, negedge H01 &&& docheck1, DMY_SPC, notifier );
$setup( posedge H03, posedge H02 &&& docheck2, DMY_SPC, notifier );
$setup( negedge H03, posedge H02 &&& docheck2, DMY_SPC, notifier );
$hold( posedge H02, posedge H03 &&& docheck2, DMY_SPC, notifier );
$hold( posedge H02, negedge H03 &&& docheck2, DMY_SPC, notifier );
$setup( posedge H04, posedge H02 &&& docheck3, DMY_SPC, notifier );
$setup( negedge H04, posedge H02 &&& docheck3, DMY_SPC, notifier );
$hold( posedge H02, posedge H04 &&& docheck3, DMY_SPC, notifier );
$hold( posedge H02, negedge H04 &&& docheck3, DMY_SPC, notifier );
$setup( posedge H05, posedge H02 &&& docheck4, DMY_SPC, notifier );
$setup( negedge H05, posedge H02 &&& docheck4, DMY_SPC, notifier );
$hold( posedge H02, posedge H05 &&& docheck4, DMY_SPC, notifier );
$hold( posedge H02, negedge H05 &&& docheck4, DMY_SPC, notifier );
$width ( posedge H02, DMY_SPC, 0, notifier );
$width ( negedge H02, DMY_SPC, 0, notifier );
( H02 *> N01 ) = ( DMY_SPC, DMY_SPC );
endspecify
endmodule
`ifdef verifault
`nosuppress_faults
`disable_portfaults
`endif
`endcelldefine