// VERSION:3.00 DATE:99/05/10 OPENCAD Verilog Library
`timescale 1ps / 1ps
`celldefine
`ifdef verifault
    `suppress_faults
`endif

primitive udp2up ( out, A, B );
    output out;
    input  A,B;
    reg    out;
    // logic for 2-input main buffer (CMOS)

    table
    //  A    B    :   out  : out + 1

        0    x    :    ?   : 0;
        0    1    :    ?   : 1;
        0    0    :    ?   : 0;

    endtable
endprimitive

`ifdef verifault
    `nosuppress_faults
`endif
`endcelldefine