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Adding Toshiba module
---------------------
1. Add toshiba module
(1) cp TC58512FT.v to TC58256FT.v and TC58128FT.v to create 16MB, 32MB toshiba devices.
The changes are:
blk_bit(parameter) changed from 12 to 11(32MB) and 10(16MB)
ID change to 9873 --- 16MB
9875 --- 32MB
(2) Create wrapper to make it behave exact same as samsung chip
(3) Read External_File.txt at time 0 and shuffle to toshiba MEM format(1024 bytes per page).
2. Change of Toshiba module
(1) Add reducing flash timing if FLASH_FAST is defined.
define tRST_program (1200)
define tRST_erase (1300)
define tRST_read (1100)
define tR (1000)
define tPROG (5000)
define tDBSY (500)
define tMBPBSY (5000)
define tBERASE (5000)
(2) Delete Toshiba "Bad-blocks"
In Toshiba's module, blocks 2/3/4 are pre-defined bad blocks.
(3) Reset_on change to 1 when Power-on.
Toshiba module needs reset command first.
(4) Spare data read.
Mask address bit 4-7 out if it is "read mode 3"
(5) Delete Toshiba "failure bits"
Toshiba pre-define the following address have single bit fail for reading.
Address bit
0 3
c00 4
ff7e0f 5
ffbe0f 6
fffe9f 7
(6) eliminate error Message
"Read Pulse width (tRP) was not proper"
"ALE Low to RE Low (tAR1) was not proper."
"Data Setup Time (tDS) was not proper"
"Write Pulse width (tWP) was not proper"
"Read Pulse width (tRP) was not proper."
if CE is not 0. (also #1 to remove race condition)
(7) Change "/CE was set to 'H' while the device was in read operation." to
"Warning" for Command terminated.
(8) Delete "Error: Timing violation tIR"
Because IO_AD is always driven. (board_id)
(9) Delete MEM_BLK4093_PAG31_XXXX defines and assigns because they are never used.
3. Changes in verilog test
(1) timeout(to) value
(2) Change parellel access to serial access
(3) Set different address phase bits for different devices.
if (flash_size >=64 ) 4'b1111
else 4'b0111.
Toshiba module is always set to 4'b1111
(4) Delete one improper test since it's already tested
line 1675:
pi_flash_start_cmd(0, 4'b1111, 8'h00);
pi_flash_reset(0);
(5) recover all ecc error page after ecc test is done.
Status:
pi_cpu_test(ecc test) and pi_dma_test interfering.
Run twice with commenting either of them out.
4. changes in system test
(1) Time (Flash_config) changed from 0x430f0f3f to 0x753e1f3f.
(2) Manufactor id changes(ifdef TOSHIBA_FLASH).
(3) Increasing response timeout(by 20%) since slower timing.
(4) Increasing busy polling timeout by 20%
(from 10000ns ==> 12000ns)
(5) Set address phase to 0xf for toshiba module.
(ifdef TOSHIBA_FLASH)
Status:
PASS @62.5MHz for samsung chip
PASS @96MHz for toshiba chip
(Chip complained timing when flash bit is set)
* This file will check in under hw/chip/lib/verilog/toshiba/flash