bl_lerp_add10.v
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////////////////////////////////////////////////////////////////////////
//
// Project Reality
//
// module: bl_lerp_add10
// description: Final carry-propigating adder for csa tree for lerp for
// blend unit. 10 bits in and out, no carry i/o.
// Conditional sum adder.
//
// designer: Phil Gossett
// date: 8/12/94
//
////////////////////////////////////////////////////////////////////////
module bl_lerp_add10 (a, b, s);
input [9:0] a;
input [9:0] b;
wire [9:0] s0b;
wire [9:0] s1b;
wire [8:0] c0b;
wire [8:0] c1b;
output [9:0] s;
// conditional cells:
xo02d1 s00 (.a1(a[0]), .a2(b[0]), .z(s[0])); // output
assign s0b[0] = s[0]; // just to avoid warning (net not driven)
assign s1b[0] = s[0]; // just to avoid warning (net not driven)
an02d1 c00 (.a1(a[0]), .a2(b[0]), .z(c0b[0]));
assign c1b[0] = c0b[0]; // just to avoid warning (net not driven)
xo02d1 s01 (.a1(a[1]), .a2(b[1]), .z(s0b[1]));
xn02d1 s11 (.a1(a[1]), .a2(b[1]), .zn(s1b[1]));
an02d1 c01 (.a1(a[1]), .a2(b[1]), .z(c0b[1]));
or02d1 c11 (.a1(a[1]), .a2(b[1]), .z(c1b[1]));
xo02d1 s02 (.a1(a[2]), .a2(b[2]), .z(s0b[2]));
xn02d1 s12 (.a1(a[2]), .a2(b[2]), .zn(s1b[2]));
an02d1 c02 (.a1(a[2]), .a2(b[2]), .z(c0b[2]));
or02d1 c12 (.a1(a[2]), .a2(b[2]), .z(c1b[2]));
xo02d1 s03 (.a1(a[3]), .a2(b[3]), .z(s0b[3]));
xn02d1 s13 (.a1(a[3]), .a2(b[3]), .zn(s1b[3]));
an02d1 c03 (.a1(a[3]), .a2(b[3]), .z(c0b[3]));
or02d1 c13 (.a1(a[3]), .a2(b[3]), .z(c1b[3]));
xo02d1 s04 (.a1(a[4]), .a2(b[4]), .z(s0b[4]));
xn02d1 s14 (.a1(a[4]), .a2(b[4]), .zn(s1b[4]));
an02d1 c04 (.a1(a[4]), .a2(b[4]), .z(c0b[4]));
or02d1 c14 (.a1(a[4]), .a2(b[4]), .z(c1b[4]));
xo02d1 s05 (.a1(a[5]), .a2(b[5]), .z(s0b[5]));
xn02d1 s15 (.a1(a[5]), .a2(b[5]), .zn(s1b[5]));
an02d1 c05 (.a1(a[5]), .a2(b[5]), .z(c0b[5]));
or02d1 c15 (.a1(a[5]), .a2(b[5]), .z(c1b[5]));
xo02d1 s06 (.a1(a[6]), .a2(b[6]), .z(s0b[6]));
xn02d1 s16 (.a1(a[6]), .a2(b[6]), .zn(s1b[6]));
an02d1 c06 (.a1(a[6]), .a2(b[6]), .z(c0b[6]));
or02d1 c16 (.a1(a[6]), .a2(b[6]), .z(c1b[6]));
xo02d1 s07 (.a1(a[7]), .a2(b[7]), .z(s0b[7]));
xn02d1 s17 (.a1(a[7]), .a2(b[7]), .zn(s1b[7]));
an02d1 c07 (.a1(a[7]), .a2(b[7]), .z(c0b[7]));
or02d1 c17 (.a1(a[7]), .a2(b[7]), .z(c1b[7]));
xo02d1 s08 (.a1(a[8]), .a2(b[8]), .z(s0b[8]));
xn02d1 s18 (.a1(a[8]), .a2(b[8]), .zn(s1b[8]));
an02d1 c08 (.a1(a[8]), .a2(b[8]), .z(c0b[8]));
or02d1 c18 (.a1(a[8]), .a2(b[8]), .z(c1b[8]));
xo02d1 s09 (.a1(a[9]), .a2(b[9]), .z(s0b[9]));
xn02d1 s19 (.a1(a[9]), .a2(b[9]), .zn(s1b[9]));
// first rank of muxes (all muxes should be high performance):
mx21d1h mas02 (.s(c0b[1]), .i0(s0b[2]), .i1(s1b[2]), .z(mas0b2));
mx21d1h mas12 (.s(c1b[1]), .i0(s0b[2]), .i1(s1b[2]), .z(mas1b2));
mx21d1h mac02 (.s(c0b[1]), .i0(c0b[2]), .i1(c1b[2]), .z(mac0b2));
mx21d1h mac12 (.s(c1b[1]), .i0(c0b[2]), .i1(c1b[2]), .z(mac1b2));
mx21d1h mas04 (.s(c0b[3]), .i0(s0b[4]), .i1(s1b[4]), .z(mas0b4));
mx21d1h mas14 (.s(c1b[3]), .i0(s0b[4]), .i1(s1b[4]), .z(mas1b4));
mx21d1h mac04 (.s(c0b[3]), .i0(c0b[4]), .i1(c1b[4]), .z(mac0b4));
mx21d1h mac14 (.s(c1b[3]), .i0(c0b[4]), .i1(c1b[4]), .z(mac1b4));
mx21d1h mas06 (.s(c0b[5]), .i0(s0b[6]), .i1(s1b[6]), .z(mas0b6));
mx21d1h mas16 (.s(c1b[5]), .i0(s0b[6]), .i1(s1b[6]), .z(mas1b6));
mx21d1h mac06 (.s(c0b[5]), .i0(c0b[6]), .i1(c1b[6]), .z(mac0b6));
mx21d1h mac16 (.s(c1b[5]), .i0(c0b[6]), .i1(c1b[6]), .z(mac1b6));
mx21d1h mas08 (.s(c0b[7]), .i0(s0b[8]), .i1(s1b[8]), .z(mas0b8));
mx21d1h mas18 (.s(c1b[7]), .i0(s0b[8]), .i1(s1b[8]), .z(mas1b8));
mx21d1h mac08 (.s(c0b[7]), .i0(c0b[8]), .i1(c1b[8]), .z(mac0b8));
mx21d1h mac18 (.s(c1b[7]), .i0(c0b[8]), .i1(c1b[8]), .z(mac1b8));
// second rank of muxes:
mx21d1h mbs01 (.s(c0b[0]), .i0(s0b[1]), .i1(s1b[1]), .z(s[1]));
mx21d1h mbs02 (.s(c0b[0]), .i0(mas0b2), .i1(mas1b2), .z(s[2]));
mx21d1h mbc02 (.s(c0b[0]), .i0(mac0b2), .i1(mac1b2), .z(mbc0b2));
mx21d1h mbs05 (.s(mac0b4), .i0(s0b[5]), .i1(s1b[5]), .z(mbs0b5));
mx21d1h mbs15 (.s(mac1b4), .i0(s0b[5]), .i1(s1b[5]), .z(mbs1b5));
mx21d1h mbs06 (.s(mac0b4), .i0(mas0b6), .i1(mas1b6), .z(mbs0b6));
mx21d1h mbs16 (.s(mac1b4), .i0(mas0b6), .i1(mas1b6), .z(mbs1b6));
mx21d1h mbc06 (.s(mac0b4), .i0(mac0b6), .i1(mac1b6), .z(mbc0b6));
mx21d1h mbc16 (.s(mac1b4), .i0(mac0b6), .i1(mac1b6), .z(mbc1b6));
mx21d1h mbs09 (.s(mac0b8), .i0(s0b[9]), .i1(s1b[9]), .z(mbs0b9));
mx21d1h mbs19 (.s(mac1b8), .i0(s0b[9]), .i1(s1b[9]), .z(mbs1b9));
// third rank of muxes:
mx21d1h mcs03 (.s(mbc0b2), .i0(s0b[3]), .i1(s1b[3]), .z(s[3]));
mx21d1h mcs04 (.s(mbc0b2), .i0(mas0b4), .i1(mas1b4), .z(s[4]));
mx21d1h mcs05 (.s(mbc0b2), .i0(mbs0b5), .i1(mbs1b5), .z(s[5]));
mx21d1h mcs06 (.s(mbc0b2), .i0(mbs0b6), .i1(mbs1b6), .z(s[6]));
mx21d1h mcc06 (.s(mbc0b2), .i0(mbc0b6), .i1(mbc1b6), .z(mcc0b6));
// fourth rank of muxes:
mx21d1h mds07 (.s(mcc0b6), .i0(s0b[7]), .i1(s1b[7]), .z(s[7]));
mx21d1h mds08 (.s(mcc0b6), .i0(mas0b8), .i1(mas1b8), .z(s[8]));
mx21d1h mds09 (.s(mcc0b6), .i0(mbs0b9), .i1(mbs1b9), .z(s[9]));
endmodule // bl_lerp_add10