/**************************************************************************
 *                                                                        *
 *               Copyright (C) 1994, Silicon Graphics, Inc.               *
 *                                                                        *
 *  These coded instructions, statements, and computer programs  contain  *
 *  unpublished  proprietary  information of Silicon Graphics, Inc., and  *
 *  are protected by Federal copyright  law.  They  may not be disclosed  *
 *  to  third  parties  or copied or duplicated in any form, in whole or  *
 *  in part, without the prior written consent of Silicon Graphics, Inc.  *
 *                                                                        *
 *************************************************************************/
// $Id: csclk.v,v 1.1 2002/03/28 00:26:13 berndt Exp $
   /////////////////////////////////////////////////////////////////////////
   //
   // Project Reality
   //
   // module:      csclk
   // description: contains fifo write pointer and fifo status which are
   //          	   computed every clk instead of every gclk
   //
   // designer:    Mike M. Cai   8/11/94
   //
   /////////////////////////////////////////////////////////////////////////

module csclk(  // outputs
      	       wr_adrs,
	       cs_xbus_req,
	       empty, cmd_busy,
	       words_fifo,
	       // inputs
	       xbus_valid,
	       read_adrs,
	       clk, reset_l
	       );
output [4:0]   wr_adrs;
output	       cs_xbus_req, empty;
output	       cmd_busy;
output [5:0]   words_fifo;
input 	       xbus_valid;
input [5:0]    read_adrs;
input 	       clk, reset_l;

reg [5:0]      w_addr_in;
wire [4:0]     wr_adrs;
reg   	       cs_xbus_req;
wire  	       empty, unrap;
reg   	       cmd_busy;
wire [5:0]     words_fifo;
wire  	       wen;

/*`ifdef jeff_smith_wants_it
   always @(w_addr_in)
      begin
      	 $display(" %h written into CDBUF", reality.rcp_0.xbus_data);
      end
`endif
*/

assign  #1 wen = xbus_valid;

always @(posedge clk or negedge reset_l)	// things sync with clk
      if (reset_l == 1'h0)	// write pointer
      	 w_addr_in <= 6'h0;
      else
      	 begin
      	    w_addr_in <= wen ? (w_addr_in + 1) : w_addr_in;
//      	    cs_xbus_req <= (words_fifo <= 6'h16);
//	    cmd_busy <= ~empty;
	 end
always @(posedge clk)
   begin
     cs_xbus_req <= (words_fifo <= 6'h16);
     cmd_busy <= ~empty; 
   end


assign  wr_adrs = w_addr_in[4:0];
assign  empty = words_fifo == 6'h0;
assign  unrap = ~w_addr_in[5] & read_adrs[5];
assign  words_fifo = {(unrap ^ w_addr_in[5]), w_addr_in[4:0]} -
      	       	      {(unrap ^ read_adrs[5]), read_adrs[4:0]};

endmodule  //  csclk