ewaddr.v
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/**************************************************************************
* *
* Copyright (C) 1994, Silicon Graphics, Inc. *
* *
* These coded instructions, statements, and computer programs contain *
* unpublished proprietary information of Silicon Graphics, Inc., and *
* are protected by Federal copyright law. They may not be disclosed *
* to third parties or copied or duplicated in any form, in whole or *
* in part, without the prior written consent of Silicon Graphics, Inc. *
* *
*************************************************************************/
// $Id: ewaddr.v,v 1.1 2002/03/28 00:26:13 berndt Exp $
/////////////////////////////////////////////////////////////////////////
//
// Project Reality
//
// module: ewaddr
// description: computes the initial address for each span
//
//
// designer: Mike M. Cai 5/13/94
//
/////////////////////////////////////////////////////////////////////////
module ewaddr( // outputs
ew_ms_addr,
// inputs
width_cimage, width_timage,
load_cmd_image,
x_sc_major, x_minor, yh,
start_mult, addr_newspan,
reset_l, gclk );
output [19:0] ew_ms_addr;
input [9:0] width_cimage, width_timage;
input load_cmd_image;
input [11:0] x_sc_major, x_minor;
input [11:0] yh;
input start_mult, addr_newspan;
input reset_l, gclk;
reg [3:0] cnt_mult;
reg [1:0] cnt_addr;
reg posy_state;
reg yh_cur;
wire mult,
add_zero,
carry_in,
sel_mult,
ld_addr;
wire [1:0] sel_addr;
reg [19:0] addr_scanline,
a_adder,
b_adder_m,
b_adder,
sum,
ew_ms_addr;
reg [9:0] a_adder_m;
reg [11:0] b_adder_a;
wire [9:0] width;
assign width = load_cmd_image ? width_timage : width_cimage;
always @(posedge gclk or negedge reset_l)
if ( reset_l == 1'h0) begin
cnt_mult <= 4'h0;
cnt_addr <= 2'h0;
posy_state <= 1'h0;
end
else
begin
cnt_mult <= (start_mult | ~((cnt_mult == 4'ha) | cnt_mult == 4'h0))
? (cnt_mult + 1) : 4'h0;
cnt_addr <= (addr_newspan | ~(cnt_addr == 2'h0))
? (cnt_addr + 1) : 2'h0;
case ({start_mult, addr_newspan, ~(yh[11] | yh[10]), posy_state})
4'h0, 4'h2, 4'h4, 4'h8, 4'h9, 4'hc, 4'hd: posy_state <= 1'h0;
4'h1, 4'h3, 4'h5, 4'h6, 4'h7, 4'ha, 4'hb,
4'he, 4'hf: posy_state <= 1'h1;
endcase
end
always @( cnt_mult or yh)
case (cnt_mult)
4'h1: yh_cur = yh[9];
4'h2: yh_cur = yh[8];
4'h3: yh_cur = yh[7];
4'h4: yh_cur = yh[6];
4'h5: yh_cur = yh[5];
4'h6: yh_cur = yh[4];
4'h7: yh_cur = yh[3];
4'h8: yh_cur = yh[2];
4'h9: yh_cur = yh[1];
4'ha: yh_cur = yh[0];
default: yh_cur = yh[0];
endcase
assign mult = ~(cnt_mult == 0);
assign add_zero = yh[11] | yh[10] | ~yh_cur;
assign sel_mult = ~((cnt_mult == 4'h0) | (cnt_mult == 4'h1));
assign ld_addr = ~(cnt_mult == 4'h0) | (cnt_addr == 2'h3);
assign sel_addr = {2{posy_state}} & (cnt_addr);
assign carry_in = (mult & ~add_zero) | (~mult & (cnt_addr == 2'h3) & posy_state);
always @(posedge gclk or negedge reset_l)
if ( reset_l == 1'h0 ) begin
addr_scanline <= 20'h0;
ew_ms_addr <= 20'h0;
end
else begin
a_adder_m = add_zero ? 10'h0 : width;
a_adder = mult ? {10'h0, a_adder_m} : addr_scanline;
b_adder_m = sel_mult ? {addr_scanline[18:0], 1'h0} : 20'h0;
case (sel_addr)
2'h0: b_adder_a = 12'h0;
2'h1: b_adder_a = x_sc_major;
2'h2: b_adder_a = x_minor;
2'h3: b_adder_a = {2'h0,width};
endcase
b_adder = mult ? b_adder_m : {8'h0, b_adder_a};
sum = a_adder + b_adder + carry_in;
addr_scanline <= ld_addr ? sum : addr_scanline;
ew_ms_addr <= sum;
end
endmodule // ewaddr