rspWrap.v
11.6 KB
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
/**************************************************************************
* *
* Copyright (C) 1994, Silicon Graphics, Inc. *
* *
* These coded instructions, statements, and computer programs contain *
* unpublished proprietary information of Silicon Graphics, Inc., and *
* are protected by Federal copyright law. They may not be disclosed *
* to third parties or copied or duplicated in any form, in whole or *
* in part, without the prior written consent of Silicon Graphics, Inc. *
* *
*************************************************************************/
// $Id: rspWrap.v,v 1.1 2002/03/28 00:26:13 berndt Exp $
// rspWrap.v: the world outside the rsp.
`timescale 1ns / 10ps
module clock(clk);
output clk;
reg clk;
initial
#2 clk = 1;
always
#8 clk = ~ clk;
endmodule
module rspWrap();
reg reset_l;
reg iddq_test;
wire clk;
integer cycleCount;
integer i;
// DMA-related IO
reg frozen;
reg sp_cbus_read_enable;
reg sp_cbus_write_enable;
reg mem_cbus_write_enable; // *** Use for CPU read of mems
reg cmd_cbus_read_enable;
reg cmd_cbus_write_enable;
reg [1:0] cbus_select;
reg [2:0] cbus_command;
reg dma_start;
reg dma_last;
reg sp_dma_grant;
reg sp_read_grant;
reg cmd_dma_grant;
reg cmd_read_grant;
reg sp_dbus_read_enable;
reg sp_dbus_write_enable;
reg cbuf_ready;
reg cmd_busy; // DP CMDBUF is not empty
reg pipe_busy; // DP pipeline is active
reg tmem_busy; // DP TMEM is loading
wire [31:0] cbus_data;
wire [63:0] dbus_data;
wire [63:0] xbus_data;
wire sp_dma_request;
wire cmd_dma_request;
wire cmd_read_request;
wire sp_read_request;
wire mem_read_request;
wire cbuf_write;
task initDMA;
begin
frozen = 1'b0;
sp_cbus_read_enable = 1'b1;
sp_cbus_write_enable = 1'b0;
mem_cbus_write_enable = 1'b0;
cmd_cbus_read_enable = 1'b1;
cmd_cbus_write_enable = 1'b0;
cbus_select = 2'b0;
cbus_command = 3'b0;
dma_start = 0;
dma_last = 0;
sp_dma_grant = 0;
sp_read_grant = 0;
cmd_dma_grant = 0;
cmd_read_grant = 0;
sp_dbus_read_enable = 0;
sp_dbus_write_enable = 0;
cbuf_ready = 0;
cmd_busy = 0;
pipe_busy = 0;
tmem_busy = 0;
end
endtask
task initSURFile;
begin
for (i=0; i<16; i=i+1) begin
rsp.su.sudp.suRFile_i.mem[i] = i;
end
rsp.su.sudp.suRFile_i.mem[0] = 32'hb00b0094;
end
endtask
task initVURFile;
begin
for (i=0; i<32; i=i+1) begin
rsp.vu.vusl01.vudp0.vdpregfile_i.mem[i] = i*16;
rsp.vu.vusl01.vudp1.vdpregfile_i.mem[i] = (i*16)+1;
rsp.vu.vusl23.vudp0.vdpregfile_i.mem[i] = (i*16)+2;
rsp.vu.vusl23.vudp1.vdpregfile_i.mem[i] = (i*16)+3;
rsp.vu.vusl45.vudp0.vdpregfile_i.mem[i] = (i*16)+4;
rsp.vu.vusl45.vudp1.vdpregfile_i.mem[i] = (i*16)+5;
rsp.vu.vusl67.vudp0.vdpregfile_i.mem[i] = (i*16)+6;
rsp.vu.vusl67.vudp1.vdpregfile_i.mem[i] = (i*16)+7;
end
end
endtask
task initIMem;
begin
$readmemh("idata", rsp.imem.ram_prim, 0);
end
endtask
// ddata 16 byte word is numbered MSB to LSB: ddata0, ddata1, ... ddata15
// dmem model 16 byte word is numbered MSB to LSB:
// high.prim7, high.prim6, ... high.prim0, low.prim7, ... low.prim0
task initDMem;
begin
$readmemh("d_0.dhex", rsp.dmemx2.dmemHigh.ram_prim7, 0);
$readmemh("d_1.dhex", rsp.dmemx2.dmemHigh.ram_prim6, 0);
$readmemh("d_2.dhex", rsp.dmemx2.dmemHigh.ram_prim5, 0);
$readmemh("d_3.dhex", rsp.dmemx2.dmemHigh.ram_prim4, 0);
$readmemh("d_4.dhex", rsp.dmemx2.dmemHigh.ram_prim3, 0);
$readmemh("d_5.dhex", rsp.dmemx2.dmemHigh.ram_prim2, 0);
$readmemh("d_6.dhex", rsp.dmemx2.dmemHigh.ram_prim1, 0);
$readmemh("d_7.dhex", rsp.dmemx2.dmemHigh.ram_prim0, 0);
$readmemh("d_8.dhex", rsp.dmemx2.dmemLow.ram_prim7, 0);
$readmemh("d_9.dhex", rsp.dmemx2.dmemLow.ram_prim6, 0);
$readmemh("d_a.dhex", rsp.dmemx2.dmemLow.ram_prim5, 0);
$readmemh("d_b.dhex", rsp.dmemx2.dmemLow.ram_prim4, 0);
$readmemh("d_c.dhex", rsp.dmemx2.dmemLow.ram_prim3, 0);
$readmemh("d_d.dhex", rsp.dmemx2.dmemLow.ram_prim2, 0);
$readmemh("d_e.dhex", rsp.dmemx2.dmemLow.ram_prim1, 0);
$readmemh("d_f.dhex", rsp.dmemx2.dmemLow.ram_prim0, 0);
end
endtask
clock clock(clk);
rsp rsp(
.clk (clk),
.reset_l (reset_l),
.iddq_test (iddq_test),
// DMA-related IO
.frozen (frozen),
.sp_cbus_read_enable (sp_cbus_read_enable),
.sp_cbus_write_enable (sp_cbus_write_enable),
.mem_cbus_write_enable (mem_cbus_write_enable),
.cmd_cbus_read_enable (cmd_cbus_read_enable),
.cmd_cbus_write_enable (cmd_cbus_write_enable),
.cbus_select (cbus_select),
.cbus_command (cbus_command),
.dma_start (dma_start),
.dma_last (dma_last),
.sp_dma_grant (sp_dma_grant),
.sp_read_grant (sp_read_grant),
.cmd_dma_grant (cmd_dma_grant),
.cmd_read_grant (cmd_read_grant),
.cbuf_ready (cbuf_ready),
.sp_dma_request (sp_dma_request),
.sp_read_request (sp_read_request),
.mem_read_request (mem_read_request),
.cmd_dma_request (cmd_dma_request),
.cmd_read_request (cmd_read_request),
.sp_dbus_read_enable (sp_dbus_read_enable),
.sp_dbus_write_enable (sp_dbus_write_enable),
.cbuf_write (cbuf_write),
.cbus_data (cbus_data),
.dbus_data (dbus_data),
.xbus_data (xbus_data)
);
initial begin
$write ("dmem[16]: %h%h%h%h %h%h%h%h %h%h%h%h %h%h%h%h \n",
rsp.dmemx2.dmemHigh.ram_prim7[1], rsp.dmemx2.dmemHigh.ram_prim6[1],
rsp.dmemx2.dmemHigh.ram_prim5[1], rsp.dmemx2.dmemHigh.ram_prim4[1],
rsp.dmemx2.dmemHigh.ram_prim3[1], rsp.dmemx2.dmemHigh.ram_prim2[1],
rsp.dmemx2.dmemHigh.ram_prim1[1], rsp.dmemx2.dmemHigh.ram_prim0[1],
rsp.dmemx2.dmemLow.ram_prim7[1], rsp.dmemx2.dmemLow.ram_prim6[1],
rsp.dmemx2.dmemLow.ram_prim5[1], rsp.dmemx2.dmemLow.ram_prim4[1],
rsp.dmemx2.dmemLow.ram_prim3[1], rsp.dmemx2.dmemLow.ram_prim2[1],
rsp.dmemx2.dmemLow.ram_prim1[1], rsp.dmemx2.dmemLow.ram_prim0[1]
);
initDMA;
initSURFile;
initVURFile;
initDMem;
initIMem;
reset_l = 0;
iddq_test = 0;
// force rsp.io_mem_dma.single_step = 0;
$dumpvars;
#30 reset_l = 1; // *** need setup time on reset_l!
end // initial
always @(posedge clk) begin
if (!reset_l) begin
cycleCount = 0;
end
else begin
cycleCount = cycleCount+1;
end
end
always @(negedge clk) begin
#2 $write ("time: %0t\tinst: %h\n", $time, rsp.su.suctl.su_inst);
$write ("imem[0]: %h \n",
rsp.imem.ram_prim[0]);
$write ("dmem[0]: %h%h%h%h %h%h%h%h %h%h%h%h %h%h%h%h \n",
rsp.dmemx2.dmemHigh.ram_prim7[0], rsp.dmemx2.dmemHigh.ram_prim6[0],
rsp.dmemx2.dmemHigh.ram_prim5[0], rsp.dmemx2.dmemHigh.ram_prim4[0],
rsp.dmemx2.dmemHigh.ram_prim3[0], rsp.dmemx2.dmemHigh.ram_prim2[0],
rsp.dmemx2.dmemHigh.ram_prim1[0], rsp.dmemx2.dmemHigh.ram_prim0[0],
rsp.dmemx2.dmemLow.ram_prim7[0], rsp.dmemx2.dmemLow.ram_prim6[0],
rsp.dmemx2.dmemLow.ram_prim5[0], rsp.dmemx2.dmemLow.ram_prim4[0],
rsp.dmemx2.dmemLow.ram_prim3[0], rsp.dmemx2.dmemLow.ram_prim2[0],
rsp.dmemx2.dmemLow.ram_prim1[0], rsp.dmemx2.dmemLow.ram_prim0[0]
);
$write ("dmem[16]: %h%h%h%h %h%h%h%h %h%h%h%h %h%h%h%h \n",
rsp.dmemx2.dmemHigh.ram_prim7[1], rsp.dmemx2.dmemHigh.ram_prim6[1],
rsp.dmemx2.dmemHigh.ram_prim5[1], rsp.dmemx2.dmemHigh.ram_prim4[1],
rsp.dmemx2.dmemHigh.ram_prim3[1], rsp.dmemx2.dmemHigh.ram_prim2[1],
rsp.dmemx2.dmemHigh.ram_prim1[1], rsp.dmemx2.dmemHigh.ram_prim0[1],
rsp.dmemx2.dmemLow.ram_prim7[1], rsp.dmemx2.dmemLow.ram_prim6[1],
rsp.dmemx2.dmemLow.ram_prim5[1], rsp.dmemx2.dmemLow.ram_prim4[1],
rsp.dmemx2.dmemLow.ram_prim3[1], rsp.dmemx2.dmemLow.ram_prim2[1],
rsp.dmemx2.dmemLow.ram_prim1[1], rsp.dmemx2.dmemLow.ram_prim0[1]
);
$write ("dmem[32]: %h%h%h%h %h%h%h%h %h%h%h%h %h%h%h%h \n",
rsp.dmemx2.dmemHigh.ram_prim7[2], rsp.dmemx2.dmemHigh.ram_prim6[2],
rsp.dmemx2.dmemHigh.ram_prim5[2], rsp.dmemx2.dmemHigh.ram_prim4[2],
rsp.dmemx2.dmemHigh.ram_prim3[2], rsp.dmemx2.dmemHigh.ram_prim2[2],
rsp.dmemx2.dmemHigh.ram_prim1[2], rsp.dmemx2.dmemHigh.ram_prim0[2],
rsp.dmemx2.dmemLow.ram_prim7[2], rsp.dmemx2.dmemLow.ram_prim6[2],
rsp.dmemx2.dmemLow.ram_prim5[2], rsp.dmemx2.dmemLow.ram_prim4[2],
rsp.dmemx2.dmemLow.ram_prim3[2], rsp.dmemx2.dmemLow.ram_prim2[2],
rsp.dmemx2.dmemLow.ram_prim1[2], rsp.dmemx2.dmemLow.ram_prim0[2]
);
$write ("dmem[48]: %h%h%h%h %h%h%h%h %h%h%h%h %h%h%h%h \n",
rsp.dmemx2.dmemHigh.ram_prim7[3], rsp.dmemx2.dmemHigh.ram_prim6[3],
rsp.dmemx2.dmemHigh.ram_prim5[3], rsp.dmemx2.dmemHigh.ram_prim4[3],
rsp.dmemx2.dmemHigh.ram_prim3[3], rsp.dmemx2.dmemHigh.ram_prim2[3],
rsp.dmemx2.dmemHigh.ram_prim1[3], rsp.dmemx2.dmemHigh.ram_prim0[3],
rsp.dmemx2.dmemLow.ram_prim7[3], rsp.dmemx2.dmemLow.ram_prim6[3],
rsp.dmemx2.dmemLow.ram_prim5[3], rsp.dmemx2.dmemLow.ram_prim4[3],
rsp.dmemx2.dmemLow.ram_prim3[3], rsp.dmemx2.dmemLow.ram_prim2[3],
rsp.dmemx2.dmemLow.ram_prim1[3], rsp.dmemx2.dmemLow.ram_prim0[3]
);
$write ("\n");
for (i=0; i<8; i=i+1) begin // display su rfile state
$write ("R%0d: %h\t R%0d: %h\t R%0d: %h\t R%0d: %h\n",
(i*4), rsp.su.sudp.suRFile_i.mem[(i*4)],
(i*4)+1, rsp.su.sudp.suRFile_i.mem[(i*4)+1],
(i*4)+2, rsp.su.sudp.suRFile_i.mem[(i*4)+2],
(i*4)+3, rsp.su.sudp.suRFile_i.mem[(i*4)+3]);
end
$write ("\n");
/*
for (i=0; i<32; i=i+1) begin // display vu rfile state
$write ("V%0d: %h %h %h %h %h %h %h %h\n",
i, rsp.vu.vudp0.vdpregfile_i.mem[i],
rsp.vu.vudp1.vdpregfile_i.mem[i],
rsp.vu.vudp2.vdpregfile_i.mem[i],
rsp.vu.vudp3.vdpregfile_i.mem[i],
rsp.vu.vudp4.vdpregfile_i.mem[i],
rsp.vu.vudp5.vdpregfile_i.mem[i],
rsp.vu.vudp6.vdpregfile_i.mem[i],
rsp.vu.vudp7.vdpregfile_i.mem[i]);
end
$write ("\n");
*/
/*
$write("vector comp code reg: %h\t vector carry out reg: %h\n",
{rsp.vu.vuctl1.vct_cmpcdhi7_ac,rsp.vu.vuctl1.vct_cmpcdhi6_ac,
rsp.vu.vuctl1.vct_cmpcdhi5_ac,rsp.vu.vuctl1.vct_cmpcdhi4_ac,
rsp.vu.vuctl1.vct_cmpcdhi3_ac,rsp.vu.vuctl1.vct_cmpcdhi2_ac,
rsp.vu.vuctl1.vct_cmpcdhi1_ac,rsp.vu.vuctl1.vct_cmpcdhi0_ac,
rsp.vu.vuctl1.vct_cmpcdlo7_ac,rsp.vu.vuctl1.vct_cmpcdlo6_ac,
rsp.vu.vuctl1.vct_cmpcdlo5_ac,rsp.vu.vuctl1.vct_cmpcdlo4_ac,
rsp.vu.vuctl1.vct_cmpcdlo3_ac,rsp.vu.vuctl1.vct_cmpcdlo2_ac,
rsp.vu.vuctl1.vct_cmpcdlo1_ac,rsp.vu.vuctl1.vct_cmpcdlo0_ac},
{rsp.vu.vuctl1.vct_opdneql7_ac,rsp.vu.vuctl1.vct_opdneql6_ac,
rsp.vu.vuctl1.vct_opdneql5_ac,rsp.vu.vuctl1.vct_opdneql4_ac,
rsp.vu.vuctl1.vct_opdneql3_ac,rsp.vu.vuctl1.vct_opdneql2_ac,
rsp.vu.vuctl1.vct_opdneql1_ac,rsp.vu.vuctl1.vct_opdneql0_ac,
rsp.vu.vuctl1.vct_cryout7_ac,rsp.vu.vuctl1.vct_cryout6_ac,
rsp.vu.vuctl1.vct_cryout5_ac,rsp.vu.vuctl1.vct_cryout4_ac,
rsp.vu.vuctl1.vct_cryout3_ac,rsp.vu.vuctl1.vct_cryout2_ac,
rsp.vu.vuctl1.vct_cryout1_ac,rsp.vu.vuctl1.vct_cryout0_ac});
$write ("\n");
*/
$write("dma dmem address: %h\n", rsp.io_mem_dma.master_address);
$write("dma rdram address: %h\n", rsp.io_mem_dma.slave_address);
$write("dma read length: %h\n", rsp.io_mem_dma.length);
end
endmodule