stz.v 2.14 KB
/**************************************************************************
 *                                                                        *
 *               Copyright (C) 1994, Silicon Graphics, Inc.               *
 *                                                                        *
 *  These coded instructions, statements, and computer programs  contain  *
 *  unpublished  proprietary  information of Silicon Graphics, Inc., and  *
 *  are protected by Federal copyright  law.  They  may not be disclosed  *
 *  to  third  parties  or copied or duplicated in any form, in whole or  *
 *  in part, without the prior written consent of Silicon Graphics, Inc.  *
 *                                                                        *
 *************************************************************************/
// $Id: stz.v,v 1.1 2002/03/28 00:26:13 berndt Exp $
/*      Project Reality
        RDP
        Created by Mike M. Cai  5/30/94
*/

module stz( att_data_out,
      	       att_data_in, dx, dy, x_offset, y_offset,
	       left_major, load, ncyc, gclk);
output [17:0]   att_data_out;
input [31:0]   att_data_in, dx;
input [21:0]   dy;
input [1:0]    x_offset, y_offset;
input 	       left_major, load, ncyc, gclk;

wire [31:0]    att_accum, dx_dir;
reg [31:0]     att_cur_s;
wire [18:0]    att_offset;
wire [17:0]     att_clamp_value;
wire [17:0]     att_clamped;
reg [17:0]     att_data_out;
reg   	       comp_new;

always @(posedge gclk)
   begin
      att_cur_s <= load ? att_data_in : att_accum;
      comp_new <= load ? ~ncyc : (ncyc ? ~comp_new : comp_new);
   end

assign  
   dx_dir = (dx ~^ {32{left_major}}) & {32{comp_new}};
adder32b adder ( .sum(att_accum), .a(att_cur_s), .b(dx_dir), 
      	       	  .ci(~left_major & comp_new));


stzoffseti dooffset ( .att_data_out(att_offset), .att_data_in(att_cur_s[31:10]),
      	       	     .dx(dx[31:10]), .dy(dy), 
		     .x_offset(x_offset), .y_offset(y_offset));

assign  
   att_clamp_value = {18{~att_offset[17]}},
   att_clamped = att_offset[18] ? att_clamp_value : att_offset[17:0];  

always @(posedge gclk)
   att_data_out <=  att_clamped;  // Z is always positive

endmodule  //  stz