tc_max_abs_dif_cry15.v
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////////////////////////////////////////////////////////////////////////
//
// Project Reality
//
// module: tc_max_abs_dif_cry15
// description: 15 bit carry-propagation for use in tc lod,
// with no carry in.
// Conditional sum style.
//
// designer: Phil Gossett
// date: 6/4/95
//
////////////////////////////////////////////////////////////////////////
// $Id: tc_max_abs_dif_cry15.v,v 1.1 2002/03/28 00:26:13 berndt Exp $
module tc_max_abs_dif_cry15 (a, b, co) ;
input [14:0] a;
input [14:0] b;
output co;
wire [14:0] c0; // carry out assuming carry in 0
wire [14:0] c1; // carry out assuming carry in 1
// conditional cells:
an02d1h c00 (.a1(a[0]), .a2(b[0]), .z(c0[0]));
assign c1[0] = c0[0];
an02d1h c01 (.a1(a[1]), .a2(b[1]), .z(c0[1]));
or02d2 c11 (.a1(a[1]), .a2(b[1]), .z(c1[1]));
an02d1h c02 (.a1(a[2]), .a2(b[2]), .z(c0[2]));
or02d2 c12 (.a1(a[2]), .a2(b[2]), .z(c1[2]));
an02d1h c03 (.a1(a[3]), .a2(b[3]), .z(c0[3]));
or02d2 c13 (.a1(a[3]), .a2(b[3]), .z(c1[3]));
an02d1h c04 (.a1(a[4]), .a2(b[4]), .z(c0[4]));
or02d2 c14 (.a1(a[4]), .a2(b[4]), .z(c1[4]));
an02d1h c05 (.a1(a[5]), .a2(b[5]), .z(c0[5]));
or02d2 c15 (.a1(a[5]), .a2(b[5]), .z(c1[5]));
an02d1h c06 (.a1(a[6]), .a2(b[6]), .z(c0[6]));
or02d2 c16 (.a1(a[6]), .a2(b[6]), .z(c1[6]));
an02d1h c07 (.a1(a[7]), .a2(b[7]), .z(c0[7]));
or02d2 c17 (.a1(a[7]), .a2(b[7]), .z(c1[7]));
an02d1h c08 (.a1(a[8]), .a2(b[8]), .z(c0[8]));
or02d2 c18 (.a1(a[8]), .a2(b[8]), .z(c1[8]));
an02d1h c09 (.a1(a[9]), .a2(b[9]), .z(c0[9]));
or02d2 c19 (.a1(a[9]), .a2(b[9]), .z(c1[9]));
an02d1h c010 (.a1(a[10]), .a2(b[10]), .z(c0[10]));
or02d2 c110 (.a1(a[10]), .a2(b[10]), .z(c1[10]));
an02d1h c011 (.a1(a[11]), .a2(b[11]), .z(c0[11]));
or02d2 c111 (.a1(a[11]), .a2(b[11]), .z(c1[11]));
an02d1h c012 (.a1(a[12]), .a2(b[12]), .z(c0[12]));
or02d2 c112 (.a1(a[12]), .a2(b[12]), .z(c1[12]));
an02d1h c013 (.a1(a[13]), .a2(b[13]), .z(c0[13]));
or02d2 c113 (.a1(a[13]), .a2(b[13]), .z(c1[13]));
an02d1h c014 (.a1(a[14]), .a2(b[14]), .z(c0[14]));
or02d2 c114 (.a1(a[14]), .a2(b[14]), .z(c1[14]));
// first rank of muxes (all muxes should be high performance):
wire m1c0b0; // carry out from bit 0
wire m1c0b2; // carry in to bit 3 assuming carry out bit 1 is 0
wire m1c1b2; // carry in to bit 3 assuming carry out bit 1 is 1
wire m1c0b4; // carry in to bit 5 assuming carry out bit 1 is 0
wire m1c1b4; // carry in to bit 5 assuming carry out bit 1 is 1
wire m1c0b6; // carry in to bit 7 assuming carry out bit 1 is 0
wire m1c1b6; // carry in to bit 7 assuming carry out bit 1 is 1
wire m1c0b8; // carry in to bit 9 assuming carry out bit 1 is 0
wire m1c1b8; // carry in to bit 9 assuming carry out bit 1 is 1
wire m1c0b10; // carry in to bit 11 assuming carry out bit 1 is 0
wire m1c1b10; // carry in to bit 11 assuming carry out bit 1 is 1
wire m1c0b12; // carry in to bit 13 assuming carry out bit 1 is 0
wire m1c1b12; // carry in to bit 13 assuming carry out bit 1 is 1
wire m1c0b14; // carry in to bit 15 assuming carry out bit 1 is 0
wire m1c1b14; // carry in to bit 15 assuming carry out bit 1 is 1
assign m1c0b0 = c0[0];
mx21d1h mx1c0b2 (.s(c0[1]), .i0(c0[2]), .i1(c1[2]), .z(m1c0b2));
mx21d1h mx1c1b2 (.s(c1[1]), .i0(c0[2]), .i1(c1[2]), .z(m1c1b2));
mx21d1h mx1c0b4 (.s(c0[3]), .i0(c0[4]), .i1(c1[4]), .z(m1c0b4));
mx21d1h mx1c1b4 (.s(c1[3]), .i0(c0[4]), .i1(c1[4]), .z(m1c1b4));
mx21d1h mx1c0b6 (.s(c0[5]), .i0(c0[6]), .i1(c1[6]), .z(m1c0b6));
mx21d1h mx1c1b6 (.s(c1[5]), .i0(c0[6]), .i1(c1[6]), .z(m1c1b6));
mx21d1h mx1c0b8 (.s(c0[7]), .i0(c0[8]), .i1(c1[8]), .z(m1c0b8));
mx21d1h mx1c1b8 (.s(c1[7]), .i0(c0[8]), .i1(c1[8]), .z(m1c1b8));
mx21d1h mx1c0b10 (.s(c0[9]), .i0(c0[10]), .i1(c1[10]), .z(m1c0b10));
mx21d1h mx1c1b10 (.s(c1[9]), .i0(c0[10]), .i1(c1[10]), .z(m1c1b10));
mx21d1h mx1c0b12 (.s(c0[11]), .i0(c0[12]), .i1(c1[12]), .z(m1c0b12));
mx21d1h mx1c1b12 (.s(c1[11]), .i0(c0[12]), .i1(c1[12]), .z(m1c1b12));
mx21d1h mx1c0b14 (.s(c0[13]), .i0(c0[14]), .i1(c1[14]), .z(m1c0b14));
mx21d1h mx1c1b14 (.s(c1[13]), .i0(c0[14]), .i1(c1[14]), .z(m1c1b14));
// second rank of muxes:
wire m2c0b2; // carry out from bit 2
wire m2c0b6; // carry in to bit 6 assuming carry out bit 4 is 0
wire m2c1b6; // carry in to bit 6 assuming carry out bit 4 is 1
wire m2c0b10; // carry in to bit 10 assuming carry out bit 8 is 0
wire m2c1b10; // carry in to bit 10 assuming carry out bit 8 is 1
wire m2c0b14; // carry in to bit 14 assuming carry out bit 12 is 0
wire m2c1b14; // carry in to bit 14 assuming carry out bit 12 is 1
mx21d1h mx2c0b2 (.s(m1c0b0), .i0(m1c0b2), .i1(m1c1b2), .z(m2c0b2));
mx21d1h mx2c0b6 (.s(m1c0b4), .i0(m1c0b6), .i1(m1c1b6), .z(m2c0b6));
mx21d1h mx2c1b6 (.s(m1c1b4), .i0(m1c0b6), .i1(m1c1b6), .z(m2c1b6));
mx21d1h mx2c0b10 (.s(m1c0b8), .i0(m1c0b10), .i1(m1c1b10), .z(m2c0b10));
mx21d1h mx2c1b10 (.s(m1c1b8), .i0(m1c0b10), .i1(m1c1b10), .z(m2c1b10));
mx21d1h mx2c0b14 (.s(m1c0b12), .i0(m1c0b14), .i1(m1c1b14), .z(m2c0b14));
mx21d1h mx2c1b14 (.s(m1c1b12), .i0(m1c0b14), .i1(m1c1b14), .z(m2c1b14));
// third rank of muxes:
wire m3c0b6; // carry out from bit 6
wire m3c0b14; // carry out of bit 14 assuming carry out bit 10 is 0
wire m3c1b14; // carry out of bit 14 assuming carry out bit 10 is 1
mx21d1h mx3c0b6 (.s(m2c0b2 ), .i0(m2c0b6), .i1(m2c1b6), .z(m3c0b6));
mx21d1h mx3c0b14 (.s(m2c0b10), .i0(m2c0b14), .i1(m2c1b14), .z(m3c0b14));
mx21d1h mx3c1b14 (.s(m2c1b10), .i0(m2c0b14), .i1(m2c1b14), .z(m3c1b14));
// fourth rank of muxes:
mx21d1h mx4c0b14 (.s(m3c0b6 ), .i0(m3c0b14), .i1(m3c1b14), .z(co));
endmodule // tc_max_abs_dif_cry15