Makefile
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#!smake -J 1
#
# This makefile has rules for making both the executables
# which make up the simulator, and for running test cases.
#
# $Revision: 1.1 $
#
COMMONPREF=rcp
PRDEPTH = /hosts/winner/usr/people/mantri/mdevroot/PR
include $(PRDEPTH)/PRdefs
#
# Directory to store verilog output files (simv, simv.daidir, csrc)
# All *.o and *.c files will be placed in $(SIMVDIR)/csrc
# User can overide this variable on make command line (i.e. make SIMVDIR=/tmp)
# or environment variable.
#
SIMVDIR = ./designc
#
# Tools
#
SIMV = LD_LIBRARY_PATH=$(VCSDIR)/lib $(SIMVDIR)/simv -q
#
# Directories
#
#
# C Sources
#
# Header file Directories
#
LCINCS =
GCINCS =
#
# Compiler options
#
OPTIMIZER = -g
LCOPTS = -fullwarn
#
# Verilog compiler options
#
# override GVCSOPTS
#
GVCSOPTS = -l vcs.log -M -Mupdate -Mmakep=pmake \
-CC "-Wab,-big_got -Wab,-dwalign" -lc -V \
LVCSOPTS = -y . \
-y $(PRDEPTH)/hw2/chip/lib/verilog/stdcell \
-y $(PRDEPTH)/hw2/chip/lib/verilog/user \
-y $(PRDEPTH)/hw2/chip/lib/verilog/udp \
+libext+.v+.vzd+.vmd \
-Mdir=$(SIMVDIR)
#
# Default Targets
#
TARGETS = simv
default install: $(TARGETS)
$(COMMONTARGS): $(COMMONPREF)$$@
$(SUBDIRS_MAKERULE)
#
# SGI/Project Reality Common Rules
#
include $(PRDEPTH)/PRrules
#
# Compile Verilog processes
#
YOGI_ROOT = /hosts/yogi/usr/people/kishor/mdevroot
simv: vec_test_ckt.v $(_FORCE)
VCS_RUNTIME=$(VCSDIR)/lib/libvcs.so \
$(VCS) $(VCSOPTS) -P $(YOGI_ROOT)/usr/lib/PR/rcppli.tab \
$(YOGI_ROOT)/usr/lib/PR/librcppli.a -o $(SIMVDIR)/$@ vec_test_ckt.v