vec_test_ckt.v
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module vec_test_clk;
reg dir_in;
trireg data ;
reg ser_data;
reg clk ;
reg tester_clk ;
integer i ,j ;
testckt_pads tst_ckt(clk,dir_in, data);
reg [9:0] word_count ;
parameter tester_half_clock_period = 16710 ;
real counter_time;
integer counter_cycle ;
parameter ring_osc_half_period = 1385;
assign data = (dir_in) ? ser_data : 1'bz ;
defparam tst_ckt.half_clock = ring_osc_half_period ;
/////////////////////////////////////////////////////////////////////
task serial_in;
input [9:0] data_word_in;
integer i ;
begin
@(posedge tester_clk) dir_in = 1'b0 ;
@(posedge tester_clk) clk = 1'b0 ;
@(posedge tester_clk) dir_in = 1'b1 ;
for(i = 0 ; i < 10 ; i = i+ 1) begin
@(posedge tester_clk) {ser_data, data_word_in} = {data_word_in, 1'b0} ;
clk = 1'b0 ;
@(posedge tester_clk) clk = 1'b1 ;
end
@(posedge tester_clk) clk = 1'b0 ;
@(posedge tester_clk) dir_in = 1'b0 ;
end
endtask
task serial_out;
input [9:0] data_word_out;
reg data_bit_out;
integer i ;
begin
@(posedge tester_clk) clk = 1'b0 ;
@(posedge tester_clk) dir_in = 1'b0 ;
for(i = 0 ; i < 10 ; i = i + 1) begin
{data_bit_out,data_word_out} = {data_word_out[9:0], 1'b0};
#1 if (data_bit_out != data)
$display ("%t : error in serial out bit %d exp:%b actu:%b",$time,i,data_bit_out,data);
@(posedge tester_clk) dir_in = 1'b1 ;
@(posedge tester_clk) dir_in = 1'b0 ;
end
end
endtask
task speed_test;
input [15:0] tester_cycles ;
begin
@(posedge tester_clk) clk = 1'b0;
@(posedge tester_clk) dir_in = 1'b0;
@(posedge tester_clk) clk = 1'b1 ;
repeat (tester_cycles) @(posedge tester_clk) ;
clk = 1'b0 ;
@(posedge tester_clk) clk = 1'b1 ;
repeat (1) @(posedge tester_clk);
end
endtask
task out_stuck_at_1_test;
reg [9:0] max_num ;
begin
max_num = (10'b0) ;
serial_in(max_num);
speed_test(15'b1);
end
endtask
////////////////////////////////////////////////////////////////////
always
begin
clk = 0 ;
tester_clk = 0;
while(1) begin
#tester_half_clock_period tester_clk = !tester_clk ;
end
end
initial
begin
serial_in(10'b00_0000_0000);
serial_out(10'b00_0000_0000);
serial_in(10'b11_1111_1111);
serial_out(10'b11_1111_1111);
serial_in(10'b01_0101_0101);
serial_out(10'b01_0101_0101);
serial_in(10'b10_1010_1010);
serial_out(10'b10_1010_1010);
out_stuck_at_1_test;
serial_in(10'b11_1110_0000);
speed_test(35);
$finish;
end
reg [15:0] cycle_cnt;
reg [16:1] data_out, data_in;
initial begin
cycle_cnt = 0;
forever @(posedge tester_clk) begin
if (dir_in == 1'b1) begin
data_out = "$Z" ;
if (data == 1'b1) data_in = "1" ;
if (data == 1'b0) data_in = "0" ;
if (data == 1'bx) data_in = "$X" ;
end
if (dir_in == 1'b0) begin
data_in = "$Z" ;
if (data == 1'b1) data_out = "1" ;
if (data == 1'b0) data_out = "0" ;
if (data == 1'bx) data_out = "$X" ;
end
$display("%d %b %s %b %s", cycle_cnt, clk,data_in,dir_in,data_out);
cycle_cnt = cycle_cnt + 1;
end
end
initial
if ($test$plusargs("dump")) $dumpvars;
endmodule