vi.v 8.25 KB
 /************************************************************************\
 *                                                                        *
 *               Copyright (C) 1994, Silicon Graphics, Inc.               *
 *                                                                        *
 *  These coded instructions, statements, and computer programs  contain  *
 *  unpublished  proprietary  information of Silicon Graphics, Inc., and  *
 *  are protected by Federal copyright  law.  They  may not be disclosed  *
 *  to  third  parties  or copied or duplicated in any form, in whole or  *
 *  in part, without the prior written consent of Silicon Graphics, Inc.  *
 *                                                                        *
 \************************************************************************/

// $Id: vi.v,v 1.1 2002/03/28 00:26:14 berndt Exp $

////////////////////////////////////////////////////////////////////////
//
// Project Reality
//
// module:	vi
// description:	Top level for video interface.
//
// designer:	Phil Gossett
// date:	5/29/95
//
////////////////////////////////////////////////////////////////////////

module vi(clk, vclk, reset_l,
   cbus_read_enable, cbus_write_enable, cbus_select, cbus_command,
   dma_start, dma_last, dma_grant, read_grant, dbus_data, ebus_data,
   dma_request, read_request, vbus_data, vbus_sync, vbus_clock_enable_l,
   vi_int, refresh_strobe, cbus_data);

`include "vi.vh"

input clk;                                   // system clock
input vclk;                                  // video clock
input reset_l;                               // system reset_l
input cbus_read_enable;                      // enable cbus read mux
input cbus_write_enable;                     // enable cbus tristate drivers
input [CBUS_SELECT_SIZE-1:0] cbus_select;    // cbus data select
input [CBUS_COMMAND_SIZE-1:0] cbus_command;  // cbus data type
input dma_start;                             // first dbus word flag
input dma_last;                              // last dbus word flag
input dma_grant;                             // DMA request granted
input read_grant;                            // read request granted
input [DBUS_DATA_SIZE-1:0] dbus_data;        // DMA bus
input [EBUS_DATA_SIZE-1:0] ebus_data;        // Extended DMA bus

output dma_request;                          // request a DMA cycle
output read_request;                         // request a read response cycle
output [VBUS_DATA_SIZE-1:0] vbus_data;       // video data out
output vbus_sync;                            // video sync out
output vbus_clock_enable_l;                  // video clock out enable
output vi_int;				     // video interrupt
output refresh_strobe;			     // == posedge(horizontal sync)

inout [CBUS_DATA_SIZE-1:0] cbus_data;        // IO bus

wire [DRAM_ADDRESS_SIZE-1:0] dma_address;
wire [DMA_LENGTH_SIZE-1:0] dma_length;
wire block_grant;
wire [CBUS_DATA_SIZE-1:0] reg_read_data;
wire [CBUS_DATA_SIZE-1:0] reg_write_data;
wire [VI_REG_ADDRESS_SIZE-1:0] reg_address;
wire reg_write_enable;

wire [16:0] ctrl;		// bits
wire [23:0] origin;		// bytes
wire [11:0] width;		// pixels
wire [9:0] v_int;		// lines
wire [9:0] v_current;		// lines
wire [7:0] hsync_width;		// pixels
wire [7:0] burst_width;		// pixels
wire [3:0] vsync_width;		// lines
wire [9:0] burst_start;		// pixels
wire [9:0] v_sync_period;	// lines
wire [11:0] h_sync_period;	// clocks
wire [4:0] leap_pattern;	// fields
wire [11:0] hsync_leap_b;	// clocks
wire [11:0] hsync_leap_a;	// clocks
wire [9:0] h_video_end;		// pixels
wire [9:0] h_video_start;	// pixels
wire [9:0] v_video_end;		// lines
wire [9:0] v_video_start;	// lines
wire [9:0] v_burst_end;		// lines
wire [9:0] v_burst_start;	// lines
wire [11:0] x_scale;		// 2.10
wire [11:0] y_scale;		// 2.10
wire [11:0] x_offset;		// 2.10
wire [11:0] y_offset;		// 2.10

wire [DRAM_ADDRESS_SIZE-1:0] block_address;
wire [DMA_LENGTH_SIZE-1:0] block_length;
wire [3:0] block_word;
wire bank_sel;
wire block_start;
wire [1:0] block_count;
wire block_partial;
wire pre_int;
wire horizontal_flag;

wire [5:0] rand;
wire [4:0] hfrac;
wire [4:0] vfrac;
wire [7:0] rgb0i;
wire [7:0] rgb1i;
wire [7:0] rgb2i;
wire [7:0] rgb3i;
wire [2:0] cvg0i;
wire [2:0] cvg1i;
wire [2:0] cvg2i;
wire [2:0] cvg3i;
wire synci;

wire wen_a;
wire wen_b;
wire [3:0] read_addr;
wire [3:0] addr_a;
wire [3:0] addr_b;
wire [EBUS_DATA_SIZE+DBUS_DATA_SIZE-1:0] data_a;
wire [EBUS_DATA_SIZE+DBUS_DATA_SIZE-1:0] data_b;
wire [EBUS_DATA_SIZE+DBUS_DATA_SIZE-1:0] din;

vi_dma vidma (.clk(clk), .reset_l(reset_l),
	.cbus_read_enable(cbus_read_enable),
	.cbus_write_enable(cbus_write_enable),
	.cbus_select(cbus_select), .cbus_command(cbus_command),
	.read_grant(read_grant), .dma_address(dma_address),
	.dma_length(dma_length), .reg_read_data(reg_read_data),

	.read_request(read_request), .reg_write_data(reg_write_data),
	.reg_address(reg_address), .reg_write_enable(reg_write_enable),
	.cbus_data(cbus_data));

vi_controller vicontroller (.clk(clk), .reset_l(reset_l),
	.dma_grant(dma_grant), .dma_start(dma_start), .dma_last(dma_last),
	.reg_write_data(reg_write_data), .reg_address(reg_address),
	.reg_write_enable(reg_write_enable), .v_current(v_current),
	.block_address(block_address), .block_length(block_length),
	.block_word(block_word), .bank_sel(bank_sel),
	.block_start(block_start), .block_count(block_count),
	.read_addr(read_addr),
	.pre_int(pre_int), .horizontal_flag(horizontal_flag),
	.di(   {dbus_data[63:48], ebus_data[7:6],
		dbus_data[47:32], ebus_data[5:4],
		dbus_data[31:16], ebus_data[3:2],
		dbus_data[15:0],  ebus_data[1:0]}),
	.dout_a(data_a), .dout_b(data_b),

	.block_partial(block_partial), .wen_a(wen_a), .wen_b(wen_b),
	.addr_a(addr_a), .addr_b(addr_b), .do(din),
	.dma_address(dma_address), .dma_length(dma_length),
	.dma_request(dma_request), .block_grant(block_grant),
	.reg_read_data(reg_read_data),
	.vbus_clock_enable_l(vbus_clock_enable_l),
	.ctrl(ctrl), .origin(origin), .width(width),
	.v_int(v_int), .hsync_width(hsync_width),
	.burst_width(burst_width), .vsync_width(vsync_width),
	.burst_start(burst_start), .v_sync_period(v_sync_period),
	.h_sync_period(h_sync_period), .leap_pattern(leap_pattern),
	.hsync_leap_b(hsync_leap_b), .hsync_leap_a(hsync_leap_a),
	.h_video_end(h_video_end), .h_video_start(h_video_start),
	.v_video_end(v_video_end), .v_video_start(v_video_start),
	.v_burst_end(v_burst_end), .v_burst_start(v_burst_start),
	.x_scale(x_scale), .y_scale(y_scale),
	.x_offset(x_offset), .y_offset(y_offset),
	.vi_int(vi_int), .refresh_strobe(refresh_strobe));

vi_sync visync (.vclk(vclk), .reset_l(reset_l),
	.type(ctrl[1:0]), .serrate(ctrl[6]), .aa_mode(ctrl[9:8]),
	.pixel_adv(ctrl[15:12]), .origin(origin), .width(width),
	.v_int(v_int), .hsync_width(hsync_width),
	.burst_width(burst_width), .vsync_width(vsync_width),
	.burst_start(burst_start), .v_sync_period(v_sync_period),
	.h_sync_period(h_sync_period), .leap_pattern(leap_pattern),
	.hsync_leap_b(hsync_leap_b), .hsync_leap_a(hsync_leap_a),
	.h_video_end(h_video_end), .h_video_start(h_video_start),
	.v_video_end(v_video_end), .v_video_start(v_video_start),
	.v_burst_end(v_burst_end), .v_burst_start(v_burst_start),
	.x_scale(x_scale), .y_scale(y_scale),
	.x_offset(x_offset), .y_offset(y_offset),
	.data_a(data_a), .data_b(data_b),
	.block_partial(block_partial), .block_grant(block_grant),

	.block_address(block_address), .block_length(block_length),
	.block_word(block_word), .bank_sel(bank_sel),
	.block_start(block_start), .block_count(block_count),
	.read_addr(read_addr),
	.pre_int(pre_int), .horizontal_flag(horizontal_flag),
	.hfrac(hfrac), .vfrac(vfrac), .v_current(v_current),
	.rgb0i(rgb0i), .rgb1i(rgb1i), .rgb2i(rgb2i), .rgb3i(rgb3i),
	.cvg0i(cvg0i), .cvg1i(cvg1i), .cvg2i(cvg2i), .cvg3i(cvg3i),
	.synci(synci));

vi_pipe vipipe (.vclk(vclk), .type(ctrl[1:0]), .aa_off(ctrl[9]),
	.dither_filter_enable(ctrl[16]), .divot_enable(ctrl[4]),
	.gamma_enable(ctrl[3]), .gamma_dither_enable(ctrl[2]),
	.rand(rand), .hfrac(hfrac), .vfrac(vfrac),
	.rgb0i(rgb0i), .rgb1i(rgb1i), .rgb2i(rgb2i), .rgb3i(rgb3i),
	.cvg0i(cvg0i), .cvg1i(cvg1i), .cvg2i(cvg2i), .cvg3i(cvg3i),
	.synci(synci),

	.srgb(vbus_data), .sync(vbus_sync));

vi_rand virand (.vclk(vclk), .reset_l(reset_l), .rand(rand));

spanbuf spanbufa (.wen(wen_a), .clk(clk), .a(addr_a),
	.di(din), .dout(data_a));

spanbuf spanbufb (.wen(wen_b), .clk(clk), .a(addr_b),
	.di(din), .dout(data_b));

endmodule