ddr_MCLK_out.rpt
6.25 KB
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****************************************
Report : timing
-path full
-delay max
-nworst 10
-max_paths 1000
Design : bb
Version: 2001.08-SP1
Date : Mon Feb 24 15:51:25 2003
****************************************
Startpoint: pllx2/CLKOA
(clock source 'MEMCLK')
Endpoint: PAD_MCLK0 (output port)
Path Group: (none)
Path Type: max
Point Incr Path
---------------------------------------------------------------
clock source latency 1.253 1.253
pllx2/CLKOA (ABPLSSCH) 0.000 1.253 r
U199/N01 (TBBUFX4) 0.278 * 1.531 r
U728/N01 (TBMXI2X1) 0.397 * 1.928 f
U170/N01 (TBNR2X1) 0.080 * 2.008 r
U172/N01 (TBNR2X1) 0.081 * 2.089 f
U168/N01 (TBINVX4) 0.359 * 2.448 r
memclk_tree/N01 (TBZI0059) 0.757 * 3.205 f
CTS_ADD2_INS_1_1/N01 (TBZI0059) 0.195 * 3.400 r
CTS_ADD2_INS_2_1/N01 (TBZI0059) 0.099 * 3.499 f
CTS_ADD2_INS_3_1/N01 (TBZI0059) 0.134 * 3.633 r
CTS_ADD2_INS_4_1/N01 (TBZI0059) 0.148 * 3.781 f
CTS_ADD2_INS_5_1/N01 (TBZI0059) 0.216 * 3.997 r
CTS_ADD2_INS_6_6/N01 (TBZI0059) 0.107 * 4.104 f
CTS_ADD2_INS_7_12/N01 (TBZI0059) 0.117 * 4.221 r
mclk_tap/N01 (TBINVX8) 0.070 * 4.291 f
mclk_buf/N01 (TBINVX8) 0.067 * 4.358 r
pad_mck0/N01 (TDBIAST2NNC2) 1.201 * 5.559 r
PAD_MCLK0 (inout) 0.000 5.559 r
data arrival time 5.559
---------------------------------------------------------------
(Path is unconstrained)
Startpoint: pllx2/CLKOA
(clock source 'MEMCLK')
Endpoint: PAD_MCLK1 (output port)
Path Group: (none)
Path Type: max
Point Incr Path
---------------------------------------------------------------
clock source latency 1.253 1.253
pllx2/CLKOA (ABPLSSCH) 0.000 1.253 r
U199/N01 (TBBUFX4) 0.278 * 1.531 r
U728/N01 (TBMXI2X1) 0.397 * 1.928 f
U170/N01 (TBNR2X1) 0.080 * 2.008 r
U172/N01 (TBNR2X1) 0.081 * 2.089 f
U168/N01 (TBINVX4) 0.359 * 2.448 r
memclk_tree/N01 (TBZI0059) 0.757 * 3.205 f
CTS_ADD2_INS_1_1/N01 (TBZI0059) 0.195 * 3.400 r
CTS_ADD2_INS_2_1/N01 (TBZI0059) 0.099 * 3.499 f
CTS_ADD2_INS_3_1/N01 (TBZI0059) 0.134 * 3.633 r
CTS_ADD2_INS_4_1/N01 (TBZI0059) 0.148 * 3.781 f
CTS_ADD2_INS_5_1/N01 (TBZI0059) 0.216 * 3.997 r
CTS_ADD2_INS_6_6/N01 (TBZI0059) 0.107 * 4.104 f
CTS_ADD2_INS_7_12/N01 (TBZI0059) 0.117 * 4.221 r
mclk_tap/N01 (TBINVX8) 0.070 * 4.291 f
pad_mck1/N01 (TDBIAST2NNC2) 1.182 * 5.473 f
PAD_MCLK1 (inout) 0.000 5.473 f
data arrival time 5.473
---------------------------------------------------------------
(Path is unconstrained)
Startpoint: pllx2/CLKOA
(clock source 'MEMCLK')
Endpoint: PAD_MCLK0 (output port)
Path Group: (none)
Path Type: max
Point Incr Path
---------------------------------------------------------------
clock source latency 1.253 1.253
pllx2/CLKOA (ABPLSSCH) 0.000 1.253 f
U199/N01 (TBBUFX4) 0.220 * 1.473 f
U728/N01 (TBMXI2X1) 0.376 * 1.849 r
U170/N01 (TBNR2X1) 0.107 * 1.956 f
U172/N01 (TBNR2X1) 0.091 * 2.047 r
U168/N01 (TBINVX4) 0.259 * 2.306 f
memclk_tree/N01 (TBZI0059) 0.704 * 3.010 r
CTS_ADD2_INS_1_1/N01 (TBZI0059) 0.197 * 3.207 f
CTS_ADD2_INS_2_1/N01 (TBZI0059) 0.099 * 3.306 r
CTS_ADD2_INS_3_1/N01 (TBZI0059) 0.133 * 3.439 f
CTS_ADD2_INS_4_1/N01 (TBZI0059) 0.147 * 3.586 r
CTS_ADD2_INS_5_1/N01 (TBZI0059) 0.222 * 3.808 f
CTS_ADD2_INS_6_6/N01 (TBZI0059) 0.109 * 3.917 r
CTS_ADD2_INS_7_12/N01 (TBZI0059) 0.121 * 4.038 f
mclk_tap/N01 (TBINVX8) 0.082 * 4.120 r
mclk_buf/N01 (TBINVX8) 0.068 * 4.188 f
pad_mck0/N01 (TDBIAST2NNC2) 1.180 * 5.368 f
PAD_MCLK0 (inout) 0.000 5.368 f
data arrival time 5.368
---------------------------------------------------------------
(Path is unconstrained)
Startpoint: pllx2/CLKOA
(clock source 'MEMCLK')
Endpoint: PAD_MCLK1 (output port)
Path Group: (none)
Path Type: max
Point Incr Path
---------------------------------------------------------------
clock source latency 1.253 1.253
pllx2/CLKOA (ABPLSSCH) 0.000 1.253 f
U199/N01 (TBBUFX4) 0.220 * 1.473 f
U728/N01 (TBMXI2X1) 0.376 * 1.849 r
U170/N01 (TBNR2X1) 0.107 * 1.956 f
U172/N01 (TBNR2X1) 0.091 * 2.047 r
U168/N01 (TBINVX4) 0.259 * 2.306 f
memclk_tree/N01 (TBZI0059) 0.704 * 3.010 r
CTS_ADD2_INS_1_1/N01 (TBZI0059) 0.197 * 3.207 f
CTS_ADD2_INS_2_1/N01 (TBZI0059) 0.099 * 3.306 r
CTS_ADD2_INS_3_1/N01 (TBZI0059) 0.133 * 3.439 f
CTS_ADD2_INS_4_1/N01 (TBZI0059) 0.147 * 3.586 r
CTS_ADD2_INS_5_1/N01 (TBZI0059) 0.222 * 3.808 f
CTS_ADD2_INS_6_6/N01 (TBZI0059) 0.109 * 3.917 r
CTS_ADD2_INS_7_12/N01 (TBZI0059) 0.121 * 4.038 f
mclk_tap/N01 (TBINVX8) 0.082 * 4.120 r
pad_mck1/N01 (TDBIAST2NNC2) 1.214 * 5.334 r
PAD_MCLK1 (inout) 0.000 5.334 r
data arrival time 5.334
---------------------------------------------------------------
(Path is unconstrained)
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