ddr_MDQS_MUX03_out.rpt
12.5 KB
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****************************************
Report : timing
-path full
-delay max
-nworst 10
-max_paths 1000
Design : bb
Version: 2001.08-SP1
Date : Mon Feb 24 15:51:35 2003
****************************************
Startpoint: pllx2/CLKOA
(clock source 'MEMCLK')
Endpoint: PAD_MDQS0 (output port)
Path Group: (none)
Path Type: max
Point Incr Path
---------------------------------------------------------------
clock source latency 1.253 1.253
pllx2/CLKOA (ABPLSSCH) 0.000 1.253 r
U199/N01 (TBBUFX4) 0.278 * 1.531 r
U728/N01 (TBMXI2X1) 0.397 * 1.928 f
U170/N01 (TBNR2X1) 0.080 * 2.008 r
U172/N01 (TBNR2X1) 0.081 * 2.089 f
U168/N01 (TBINVX4) 0.359 * 2.448 r
memclk_tree/N01 (TBZI0059) 0.757 * 3.205 f
CTS_ADD2_INS_1_1/N01 (TBZI0059) 0.195 * 3.400 r
CTS_ADD2_INS_2_2/N01 (TBZI0059) 0.094 * 3.494 f
CTS_ADD2_INS_3_3/N01 (TBZI0059) 0.094 * 3.588 r
CTS_ADD2_INS_4_2/N01 (TBZI0059) 0.138 * 3.726 f
CTS_ADD2_INS_5_10/N01 (TBZI0059) 0.183 * 3.909 r
CTS_ADD2_INS_6_24/N01 (TBZI0059) 0.291 * 4.200 f
CTS_ADD2_INS_7_102/N01 (TBZI0059) 0.109 * 4.309 r
ddr_somux0/H03 (TBMXI2X4) <- 0.008 * 4.317 r
ddr_somux0/N01 (TBMXI2X4) 0.079 * 4.396 r
pad_dqs0/N01 (TDBIAST2NNC1) 2.996 * 7.392 r
PAD_MDQS0 (inout) 0.000 7.392 r
data arrival time 7.392
---------------------------------------------------------------
(Path is unconstrained)
Startpoint: pllx2/CLKOA
(clock source 'MEMCLK')
Endpoint: PAD_MDQS3 (output port)
Path Group: (none)
Path Type: max
Point Incr Path
---------------------------------------------------------------
clock source latency 1.253 1.253
pllx2/CLKOA (ABPLSSCH) 0.000 1.253 r
U199/N01 (TBBUFX4) 0.278 * 1.531 r
U728/N01 (TBMXI2X1) 0.397 * 1.928 f
U170/N01 (TBNR2X1) 0.080 * 2.008 r
U172/N01 (TBNR2X1) 0.081 * 2.089 f
U168/N01 (TBINVX4) 0.359 * 2.448 r
memclk_tree/N01 (TBZI0059) 0.757 * 3.205 f
CTS_ADD2_INS_1_1/N01 (TBZI0059) 0.195 * 3.400 r
CTS_ADD2_INS_2_2/N01 (TBZI0059) 0.094 * 3.494 f
CTS_ADD2_INS_3_3/N01 (TBZI0059) 0.094 * 3.588 r
CTS_ADD2_INS_4_3/N01 (TBZI0059) 0.141 * 3.729 f
CTS_ADD2_INS_5_3/N01 (TBZI0059) 0.196 * 3.925 r
CTS_ADD2_INS_6_3/N01 (TBZI0059) 0.149 * 4.074 f
CTS_ADD2_INS_7_21/N01 (TBZI0059) 0.151 * 4.225 r
ddr_somux3/H03 (TBMXI2X4) <- 0.045 * 4.270 r
ddr_somux3/N01 (TBMXI2X4) 0.101 * 4.371 r
pad_dqs3/N01 (TDBIAST2NNC1) 2.982 * 7.353 r
PAD_MDQS3 (inout) 0.000 7.353 r
data arrival time 7.353
---------------------------------------------------------------
(Path is unconstrained)
Startpoint: pllx2/CLKOA
(clock source 'MEMCLK')
Endpoint: PAD_MDQS1 (output port)
Path Group: (none)
Path Type: max
Point Incr Path
---------------------------------------------------------------
clock source latency 1.253 1.253
pllx2/CLKOA (ABPLSSCH) 0.000 1.253 r
U199/N01 (TBBUFX4) 0.278 * 1.531 r
U728/N01 (TBMXI2X1) 0.397 * 1.928 f
U170/N01 (TBNR2X1) 0.080 * 2.008 r
U172/N01 (TBNR2X1) 0.081 * 2.089 f
U168/N01 (TBINVX4) 0.359 * 2.448 r
memclk_tree/N01 (TBZI0059) 0.757 * 3.205 f
CTS_ADD2_INS_1_1/N01 (TBZI0059) 0.195 * 3.400 r
CTS_ADD2_INS_2_1/N01 (TBZI0059) 0.099 * 3.499 f
CTS_ADD2_INS_3_1/N01 (TBZI0059) 0.134 * 3.633 r
CTS_ADD2_INS_4_4/N01 (TBZI0059) 0.094 * 3.727 f
CTS_ADD2_INS_5_4/N01 (TBZI0059) 0.208 * 3.935 r
CTS_ADD2_INS_6_8/N01 (TBZI0059) 0.143 * 4.078 f
CTS_ADD2_INS_7_14/N01 (TBZI0059) 0.165 * 4.243 r
ddr_somux1/H03 (TBMXI2X4) <- 0.008 * 4.251 r
ddr_somux1/N01 (TBMXI2X4) 0.098 * 4.349 r
pad_dqs1/N01 (TDBIAST2NNC1) 2.966 * 7.315 r
PAD_MDQS1 (inout) 0.000 7.315 r
data arrival time 7.315
---------------------------------------------------------------
(Path is unconstrained)
Startpoint: pllx2/CLKOA
(clock source 'MEMCLK')
Endpoint: PAD_MDQS2 (output port)
Path Group: (none)
Path Type: max
Point Incr Path
---------------------------------------------------------------
clock source latency 1.253 1.253
pllx2/CLKOA (ABPLSSCH) 0.000 1.253 r
U199/N01 (TBBUFX4) 0.278 * 1.531 r
U728/N01 (TBMXI2X1) 0.397 * 1.928 f
U170/N01 (TBNR2X1) 0.080 * 2.008 r
U172/N01 (TBNR2X1) 0.081 * 2.089 f
U168/N01 (TBINVX4) 0.359 * 2.448 r
memclk_tree/N01 (TBZI0059) 0.757 * 3.205 f
CTS_ADD2_INS_1_1/N01 (TBZI0059) 0.195 * 3.400 r
CTS_ADD2_INS_2_2/N01 (TBZI0059) 0.094 * 3.494 f
CTS_ADD2_INS_3_2/N01 (TBZI0059) 0.107 * 3.601 r
CTS_ADD2_INS_4_6/N01 (TBZI0059) 0.251 * 3.852 f
CTS_ADD2_INS_5_9/N01 (TBZI0059) 0.127 * 3.979 r
CTS_ADD2_INS_6_34/N01 (TBZI0059) 0.130 * 4.109 f
CTS_ADD2_INS_7_108/N01 (TBZI0059) 0.112 * 4.221 r
ddr_somux2/H03 (TBMXI2X4) <- 0.009 * 4.230 r
ddr_somux2/N01 (TBMXI2X4) 0.083 * 4.313 r
pad_dqs2/N01 (TDBIAST2NNC1) 2.984 * 7.297 r
PAD_MDQS2 (inout) 0.000 7.297 r
data arrival time 7.297
---------------------------------------------------------------
(Path is unconstrained)
Startpoint: pllx2/CLKOA
(clock source 'MEMCLK')
Endpoint: PAD_MDQS0 (output port)
Path Group: (none)
Path Type: max
Point Incr Path
---------------------------------------------------------------
clock source latency 1.253 1.253
pllx2/CLKOA (ABPLSSCH) 0.000 1.253 f
U199/N01 (TBBUFX4) 0.220 * 1.473 f
U728/N01 (TBMXI2X1) 0.376 * 1.849 r
U170/N01 (TBNR2X1) 0.107 * 1.956 f
U172/N01 (TBNR2X1) 0.091 * 2.047 r
U168/N01 (TBINVX4) 0.259 * 2.306 f
memclk_tree/N01 (TBZI0059) 0.704 * 3.010 r
CTS_ADD2_INS_1_1/N01 (TBZI0059) 0.197 * 3.207 f
CTS_ADD2_INS_2_2/N01 (TBZI0059) 0.093 * 3.300 r
CTS_ADD2_INS_3_3/N01 (TBZI0059) 0.093 * 3.393 f
CTS_ADD2_INS_4_2/N01 (TBZI0059) 0.139 * 3.532 r
CTS_ADD2_INS_5_10/N01 (TBZI0059) 0.189 * 3.721 f
CTS_ADD2_INS_6_24/N01 (TBZI0059) 0.293 * 4.014 r
CTS_ADD2_INS_7_102/N01 (TBZI0059) 0.112 * 4.126 f
ddr_somux0/H03 (TBMXI2X4) <- 0.008 * 4.134 f
ddr_somux0/N01 (TBMXI2X4) 0.151 * 4.285 f
pad_dqs0/N01 (TDBIAST2NNC1) 1.265 * 5.550 f
PAD_MDQS0 (inout) 0.000 5.550 f
data arrival time 5.550
---------------------------------------------------------------
(Path is unconstrained)
Startpoint: pllx2/CLKOA
(clock source 'MEMCLK')
Endpoint: PAD_MDQS3 (output port)
Path Group: (none)
Path Type: max
Point Incr Path
---------------------------------------------------------------
clock source latency 1.253 1.253
pllx2/CLKOA (ABPLSSCH) 0.000 1.253 f
U199/N01 (TBBUFX4) 0.220 * 1.473 f
U728/N01 (TBMXI2X1) 0.376 * 1.849 r
U170/N01 (TBNR2X1) 0.107 * 1.956 f
U172/N01 (TBNR2X1) 0.091 * 2.047 r
U168/N01 (TBINVX4) 0.259 * 2.306 f
memclk_tree/N01 (TBZI0059) 0.704 * 3.010 r
CTS_ADD2_INS_1_1/N01 (TBZI0059) 0.197 * 3.207 f
CTS_ADD2_INS_2_2/N01 (TBZI0059) 0.093 * 3.300 r
CTS_ADD2_INS_3_3/N01 (TBZI0059) 0.093 * 3.393 f
CTS_ADD2_INS_4_3/N01 (TBZI0059) 0.142 * 3.535 r
CTS_ADD2_INS_5_3/N01 (TBZI0059) 0.201 * 3.736 f
CTS_ADD2_INS_6_3/N01 (TBZI0059) 0.149 * 3.885 r
CTS_ADD2_INS_7_21/N01 (TBZI0059) 0.159 * 4.044 f
ddr_somux3/H03 (TBMXI2X4) <- 0.045 * 4.089 f
ddr_somux3/N01 (TBMXI2X4) 0.172 * 4.261 f
pad_dqs3/N01 (TDBIAST2NNC1) 1.263 * 5.524 f
PAD_MDQS3 (inout) 0.000 5.524 f
data arrival time 5.524
---------------------------------------------------------------
(Path is unconstrained)
Startpoint: pllx2/CLKOA
(clock source 'MEMCLK')
Endpoint: PAD_MDQS1 (output port)
Path Group: (none)
Path Type: max
Point Incr Path
---------------------------------------------------------------
clock source latency 1.253 1.253
pllx2/CLKOA (ABPLSSCH) 0.000 1.253 f
U199/N01 (TBBUFX4) 0.220 * 1.473 f
U728/N01 (TBMXI2X1) 0.376 * 1.849 r
U170/N01 (TBNR2X1) 0.107 * 1.956 f
U172/N01 (TBNR2X1) 0.091 * 2.047 r
U168/N01 (TBINVX4) 0.259 * 2.306 f
memclk_tree/N01 (TBZI0059) 0.704 * 3.010 r
CTS_ADD2_INS_1_1/N01 (TBZI0059) 0.197 * 3.207 f
CTS_ADD2_INS_2_1/N01 (TBZI0059) 0.099 * 3.306 r
CTS_ADD2_INS_3_1/N01 (TBZI0059) 0.133 * 3.439 f
CTS_ADD2_INS_4_4/N01 (TBZI0059) 0.090 * 3.529 r
CTS_ADD2_INS_5_4/N01 (TBZI0059) 0.210 * 3.739 f
CTS_ADD2_INS_6_8/N01 (TBZI0059) 0.144 * 3.883 r
CTS_ADD2_INS_7_14/N01 (TBZI0059) 0.173 * 4.056 f
ddr_somux1/H03 (TBMXI2X4) <- 0.009 * 4.065 f
ddr_somux1/N01 (TBMXI2X4) 0.178 * 4.243 f
pad_dqs1/N01 (TDBIAST2NNC1) 1.261 * 5.504 f
PAD_MDQS1 (inout) 0.000 5.504 f
data arrival time 5.504
---------------------------------------------------------------
(Path is unconstrained)
Startpoint: pllx2/CLKOA
(clock source 'MEMCLK')
Endpoint: PAD_MDQS2 (output port)
Path Group: (none)
Path Type: max
Point Incr Path
---------------------------------------------------------------
clock source latency 1.253 1.253
pllx2/CLKOA (ABPLSSCH) 0.000 1.253 f
U199/N01 (TBBUFX4) 0.220 * 1.473 f
U728/N01 (TBMXI2X1) 0.376 * 1.849 r
U170/N01 (TBNR2X1) 0.107 * 1.956 f
U172/N01 (TBNR2X1) 0.091 * 2.047 r
U168/N01 (TBINVX4) 0.259 * 2.306 f
memclk_tree/N01 (TBZI0059) 0.704 * 3.010 r
CTS_ADD2_INS_1_1/N01 (TBZI0059) 0.197 * 3.207 f
CTS_ADD2_INS_2_2/N01 (TBZI0059) 0.093 * 3.300 r
CTS_ADD2_INS_3_2/N01 (TBZI0059) 0.106 * 3.406 f
CTS_ADD2_INS_4_6/N01 (TBZI0059) 0.251 * 3.657 r
CTS_ADD2_INS_5_9/N01 (TBZI0059) 0.128 * 3.785 f
CTS_ADD2_INS_6_34/N01 (TBZI0059) 0.127 * 3.912 r
CTS_ADD2_INS_7_108/N01 (TBZI0059) 0.116 * 4.028 f
ddr_somux2/H03 (TBMXI2X4) <- 0.009 * 4.037 f
ddr_somux2/N01 (TBMXI2X4) 0.151 * 4.188 f
pad_dqs2/N01 (TDBIAST2NNC1) 1.263 * 5.451 f
PAD_MDQS2 (inout) 0.000 5.451 f
data arrival time 5.451
---------------------------------------------------------------
(Path is unconstrained)
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