usbclk.tcl
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#################################
# USBCLK (MAX:48MHz) #
#################################
create_clock \
-name USBCLK \
-period 19.6 \
-waveform [ list 0.0 9.8 ] \
[ get_ports PAD_USBCLKI ]
set_propagated_clock \
[ get_clocks USBCLK ]
#
# usb;
# dont_touch transceiver cells;
# output jitter is spec'ed at -2..5, constrain to 5ns;
#
set usbclk_latency_max 100000
foreach_in_collection cur_path \
[ get_timing_paths -nworst 10000 -max_paths 10000 \
-from [get_ports PAD_USBCLKI] \
-to [get_pins */*/*/*/*/*reg*/H02] \
-delay max_rise \
] {
set cur_delay [ get_attribute $cur_path arrival ]
set cur_end [ get_attribute $cur_path endpoint ]
set cur_name [ get_attribute $cur_end full_name ]
echo [ format "%s : %s" $cur_name $cur_delay ]
if {$cur_delay < $usbclk_latency_max} { set usbclk_latency_max $cur_delay }
}
echo [ format "usbclk_latency_max : %s" $usbclk_latency_max ]
set_output_delay [ expr 6.0 - $usbclk_latency_max ] -clock USBCLK -max [list PAD_USB_DPLUS0 PAD_USB_DMINUS0]
set_output_delay [ expr 6.0 - $usbclk_latency_max ] -clock USBCLK -max [list PAD_USB_DPLUS1 PAD_USB_DMINUS1]
set_input_delay [ expr 6.0 + $usbclk_latency_max ] -clock USBCLK -max [list PAD_USB_DPLUS0 PAD_USB_DMINUS0]
set_input_delay [ expr 6.0 + $usbclk_latency_max ] -clock USBCLK -max [list PAD_USB_DPLUS1 PAD_USB_DMINUS1]
###set_output_delay 1.0 -clock USBCLK -min [list PAD_USB_DPLUS0 PAD_USB_DMINUS0]
###set_output_delay 1.0 -clock USBCLK -min [list PAD_USB_DPLUS1 PAD_USB_DMINUS1]