#################################
# MEMCLK (200MHz from PLL)      #
#################################


# Get delay from pllx2/CLKOA to flipflop ------------------------

   set memclk_latency_max 100000
   foreach_in_collection cur_path \
       [ get_timing_paths -nworst 10000 -max_paths 10000 \
         -from [ get_pins pllx2/CLKOA ] \
         -to   [ get_pins ddr_do*reg*/H02 ] \
         -delay max_rise \
       ] {
           set cur_delay [ get_attribute $cur_path arrival   ]
           set cur_end   [ get_attribute $cur_path endpoint  ]
           set cur_name  [ get_attribute $cur_end  full_name ]
           echo [ format "%s : %s" $cur_name $cur_delay ]
           if {$cur_delay < $memclk_latency_max} { set memclk_latency_max $cur_delay }

   }
   echo [ format "memclk_latency_max : %s" $memclk_latency_max ]

   set memclk_latency_min 0
   foreach_in_collection cur_path \
       [ get_timing_paths -nworst 10000 -max_paths 10000 \
         -from [ get_pins pllx2/CLKOA ] \
         -to   [ get_pins ddr_do*reg*/H02 ] \
         -delay min_rise \
       ] {
           set cur_delay [ get_attribute $cur_path arrival   ]
           set cur_end   [ get_attribute $cur_path endpoint  ]
           set cur_name  [ get_attribute $cur_end  full_name ]
           echo [ format "%s : %s" $cur_name $cur_delay ]
           if {$cur_delay > $memclk_latency_min} { set memclk_latency_min $cur_delay }

   }
   echo [ format "memclk_latency_min : %s" $memclk_latency_min ]


# Create MEMCLK --------------------------------------------------

create_clock \
 -name MEMCLK \
 -period 4.9 \
 -waveform [ list [expr 0.0 + $memclk_latency_max] [expr 2.45 + $memclk_latency_max ] ] \
 [ get_pins pllx2/CLKOA ]

set_propagated_clock \
 [ get_clocks MEMCLK ]


# PLL Offset/Jitter ( ABPLSSCH Specification ) -------------------
####set offset_minus 0.060
####set offset_plus  0.120
####set jitter_minus 0.100
####set jitter_plus  0.100

# Disalble Timing Arc from PLL lib -------------------------------
set_disable_timing -from ATBI0 -to CLKOA analog/ABPLSSCH
set_disable_timing -from ATBI0 -to CLKOB analog/ABPLSSCH
set_disable_timing -from ATBI0 -to CLKOC analog/ABPLSSCH


# Get delay from PAD_SYSCLK to pllx2/RCLK ------------------------

   set in_to_pll_path_max \
     [ get_timing_paths \
          -from [get_ports PAD_SYSCLK] \
          -to [get_pins pllx2/RCLK] \
          -delay max_rise \
     ]

   set indelay_pll \
     [ get_attribute $in_to_pll_path_max arrival ]

   set in_to_pll_path_min \
     [ get_timing_paths \
          -from [get_ports PAD_SYSCLK] \
          -to [get_pins pllx2/RCLK] \
          -delay min_rise \
     ]

   set indelay_pll_min \
     [ get_attribute $in_to_pll_path_min arrival ]




# Get delay from pllx2/CLKOA to pllx2/CLKI -----------------------
# PLL adjusts phase of RCLK and CLKI -----------------------------

   set feedback_pll_path \
     [ get_timing_paths \
          -from [get_pins pllx2/CLKOA] \
          -to [get_pins pllx2/CLKI] \
          -delay max_rise \
     ]

   set pll_feedback_delay \
     [ get_attribute $feedback_pll_path arrival ]

   set_clock_latency -source \
     [ expr $indelay_pll - $pll_feedback_delay  ] \
     [ get_clocks MEMCLK ]


#
#  ddr diff clock to pins;
#  memclk -> buf -> ( buf -> io -> pin, inv -> io -> pin );
#  tap off memclk tree only once to eliminate memclk tree skew;
#  dont_touch all involved cells and wires;
#  PAD_* and pad_* are already dont_touch above;
# 



set_max_delay 1.3  -from MEMCLK -to [list PAD_MCLK0 PAD_MCLK1]
set_min_delay 1.1  -from MEMCLK -to [list PAD_MCLK0 PAD_MCLK1]


#/*
# * create virtual clock at DDR chip;
# * delayed by t[out] + board delay of 1/4 memclk;
# * set to uncertainty of memclk;
# */
create_clock -name DDRCLK -period 4.9 -waveform [list 2.45 4.9] 
set_clock_uncertainty 0.250 DDRCLK


#/*
# * ddr address/ctrl path;
# * single-data rate, outputs synchronous to MEMCLK;
# * remember that DDR sees delayed clock;
# */
set_output_delay 2.6 -clock DDRCLK -max [get_ports PAD_MBANK*]
set_output_delay 2.6 -clock DDRCLK -max [get_ports PAD_MADDR*]
set_output_delay 2.6 -clock DDRCLK -max [list PAD_MRAS PAD_MCAS PAD_MWE PAD_MCKE]


#/*
# * ddr output data path;
# * double-date rate, synchronous to MEMCLK;
# * remember that DDR sees delayed clock;
# * strobes have board delays to center data;
# */
set_min_delay 1.2 -from MEMCLK -to PAD_MDATA0
set_min_delay 1.2 -from MEMCLK -to PAD_MDATA1
set_min_delay 1.2 -from MEMCLK -to PAD_MDATA2
set_min_delay 1.2 -from MEMCLK -to PAD_MDATA3
set_min_delay 1.2 -from MEMCLK -to PAD_MDATA4
set_min_delay 1.2 -from MEMCLK -to PAD_MDATA5
set_min_delay 1.2 -from MEMCLK -to PAD_MDATA6
set_min_delay 1.2 -from MEMCLK -to PAD_MDATA7
set_min_delay 1.2 -from MEMCLK -to PAD_MDATA8
set_min_delay 1.2 -from MEMCLK -to PAD_MDATA9
set_min_delay 1.2 -from MEMCLK -to PAD_MDATA10
set_min_delay 1.2 -from MEMCLK -to PAD_MDATA11
set_min_delay 1.2 -from MEMCLK -to PAD_MDATA12
set_min_delay 1.2 -from MEMCLK -to PAD_MDATA13
set_min_delay 1.2 -from MEMCLK -to PAD_MDATA14
set_min_delay 1.2 -from MEMCLK -to PAD_MDATA15
set_min_delay 1.2 -from MEMCLK -to PAD_MDATA16
set_min_delay 1.2 -from MEMCLK -to PAD_MDATA17
set_min_delay 1.2 -from MEMCLK -to PAD_MDATA18
set_min_delay 1.2 -from MEMCLK -to PAD_MDATA19
set_min_delay 1.2 -from MEMCLK -to PAD_MDATA20
set_min_delay 1.2 -from MEMCLK -to PAD_MDATA21
set_min_delay 1.2 -from MEMCLK -to PAD_MDATA22
set_min_delay 1.2 -from MEMCLK -to PAD_MDATA23
set_min_delay 1.2 -from MEMCLK -to PAD_MDATA24
set_min_delay 1.2 -from MEMCLK -to PAD_MDATA25
set_min_delay 1.2 -from MEMCLK -to PAD_MDATA26
set_min_delay 1.2 -from MEMCLK -to PAD_MDATA27
set_min_delay 1.2 -from MEMCLK -to PAD_MDATA28
set_min_delay 1.2 -from MEMCLK -to PAD_MDATA29
set_min_delay 1.2 -from MEMCLK -to PAD_MDATA30
set_min_delay 1.2 -from MEMCLK -to PAD_MDATA31
set_min_delay 1.2 -from MEMCLK -to PAD_MDQM0
set_min_delay 1.2 -from MEMCLK -to PAD_MDQM1
set_min_delay 1.2 -from MEMCLK -to PAD_MDQM2
set_min_delay 1.2 -from MEMCLK -to PAD_MDQM3

set_min_delay 1.2 -from MEMCLK -to PAD_MDQS0
set_min_delay 1.2 -from MEMCLK -to PAD_MDQS1
set_min_delay 1.2 -from MEMCLK -to PAD_MDQS2
set_min_delay 1.2 -from MEMCLK -to PAD_MDQS3
set_min_delay 1.4 -from ddr_wr_n_reg -to PAD_MDQS0
set_min_delay 1.4 -from ddr_wr_n_reg -to PAD_MDQS1
set_min_delay 1.4 -from ddr_wr_n_reg -to PAD_MDQS2
set_min_delay 1.4 -from ddr_wr_n_reg -to PAD_MDQS3

set_min_delay 1.4 -from [list ddr_do_p_reg_0_ ddr_do_n_reg_0_] -to PAD_MDATA0
set_min_delay 1.4 -from [list ddr_do_p_reg_1_ ddr_do_n_reg_1_] -to PAD_MDATA1
set_min_delay 1.4 -from [list ddr_do_p_reg_2_ ddr_do_n_reg_2_] -to PAD_MDATA2
set_min_delay 1.4 -from [list ddr_do_p_reg_3_ ddr_do_n_reg_3_] -to PAD_MDATA3
set_min_delay 1.4 -from [list ddr_do_p_reg_4_ ddr_do_n_reg_4_] -to PAD_MDATA4
set_min_delay 1.4 -from [list ddr_do_p_reg_5_ ddr_do_n_reg_5_] -to PAD_MDATA5
set_min_delay 1.4 -from [list ddr_do_p_reg_6_ ddr_do_n_reg_6_] -to PAD_MDATA6
set_min_delay 1.4 -from [list ddr_do_p_reg_7_ ddr_do_n_reg_7_] -to PAD_MDATA7
set_min_delay 1.4 -from [list ddr_do_p_reg_8_ ddr_do_n_reg_8_] -to PAD_MDATA8
set_min_delay 1.4 -from [list ddr_do_p_reg_9_ ddr_do_n_reg_9_] -to PAD_MDATA9
set_min_delay 1.4 -from [list ddr_do_p_reg_10_ ddr_do_n_reg_10_] -to PAD_MDATA10
set_min_delay 1.4 -from [list ddr_do_p_reg_11_ ddr_do_n_reg_11_] -to PAD_MDATA11
set_min_delay 1.4 -from [list ddr_do_p_reg_12_ ddr_do_n_reg_12_] -to PAD_MDATA12
set_min_delay 1.4 -from [list ddr_do_p_reg_13_ ddr_do_n_reg_13_] -to PAD_MDATA13
set_min_delay 1.4 -from [list ddr_do_p_reg_14_ ddr_do_n_reg_14_] -to PAD_MDATA14
set_min_delay 1.4 -from [list ddr_do_p_reg_15_ ddr_do_n_reg_15_] -to PAD_MDATA15
set_min_delay 1.4 -from [list ddr_do_p_reg_16_ ddr_do_n_reg_16_] -to PAD_MDATA16
set_min_delay 1.4 -from [list ddr_do_p_reg_17_ ddr_do_n_reg_17_] -to PAD_MDATA17
set_min_delay 1.4 -from [list ddr_do_p_reg_18_ ddr_do_n_reg_18_] -to PAD_MDATA18
set_min_delay 1.4 -from [list ddr_do_p_reg_19_ ddr_do_n_reg_19_] -to PAD_MDATA19
set_min_delay 1.4 -from [list ddr_do_p_reg_20_ ddr_do_n_reg_20_] -to PAD_MDATA20
set_min_delay 1.4 -from [list ddr_do_p_reg_21_ ddr_do_n_reg_21_] -to PAD_MDATA21
set_min_delay 1.4 -from [list ddr_do_p_reg_22_ ddr_do_n_reg_22_] -to PAD_MDATA22
set_min_delay 1.4 -from [list ddr_do_p_reg_23_ ddr_do_n_reg_23_] -to PAD_MDATA23
set_min_delay 1.4 -from [list ddr_do_p_reg_24_ ddr_do_n_reg_24_] -to PAD_MDATA24
set_min_delay 1.4 -from [list ddr_do_p_reg_25_ ddr_do_n_reg_25_] -to PAD_MDATA25
set_min_delay 1.4 -from [list ddr_do_p_reg_26_ ddr_do_n_reg_26_] -to PAD_MDATA26
set_min_delay 1.4 -from [list ddr_do_p_reg_27_ ddr_do_n_reg_27_] -to PAD_MDATA27
set_min_delay 1.4 -from [list ddr_do_p_reg_28_ ddr_do_n_reg_28_] -to PAD_MDATA28
set_min_delay 1.4 -from [list ddr_do_p_reg_29_ ddr_do_n_reg_29_] -to PAD_MDATA29
set_min_delay 1.4 -from [list ddr_do_p_reg_30_ ddr_do_n_reg_30_] -to PAD_MDATA30
set_min_delay 1.4 -from [list ddr_do_p_reg_31_ ddr_do_n_reg_31_] -to PAD_MDATA31
set_min_delay 1.4 -from [list ddr_dqm_p_reg_0_ ddr_dqm_n_reg_0_] -to PAD_MDQM0
set_min_delay 1.4 -from [list ddr_dqm_p_reg_1_ ddr_dqm_n_reg_1_] -to PAD_MDQM1
set_min_delay 1.4 -from [list ddr_dqm_p_reg_2_ ddr_dqm_n_reg_2_] -to PAD_MDQM2
set_min_delay 1.4 -from [list ddr_dqm_p_reg_3_ ddr_dqm_n_reg_3_] -to PAD_MDQM3

set_min_delay 1.4 -from ddr_moe_reg_0_ -to [list PAD_MDATA0 PAD_MDATA1 PAD_MDATA2 PAD_MDATA3 PAD_MDQS0]
set_min_delay 1.4 -from ddr_moe_reg_1_ -to [list PAD_MDATA4 PAD_MDATA5 PAD_MDATA6 PAD_MDATA7]
set_min_delay 1.4 -from ddr_moe_reg_2_ -to [list PAD_MDATA8 PAD_MDATA9 PAD_MDATA10 PAD_MDATA11 PAD_MDQS1]
set_min_delay 1.4 -from ddr_moe_reg_3_ -to [list PAD_MDATA12 PAD_MDATA13 PAD_MDATA14 PAD_MDATA15]
set_min_delay 1.4 -from ddr_moe_reg_4_ -to [list PAD_MDATA16 PAD_MDATA17 PAD_MDATA18 PAD_MDATA19 PAD_MDQS2]
set_min_delay 1.4 -from ddr_moe_reg_5_ -to [list PAD_MDATA20 PAD_MDATA21 PAD_MDATA22 PAD_MDATA23]
set_min_delay 1.4 -from ddr_moe_reg_6_ -to [list PAD_MDATA24 PAD_MDATA25 PAD_MDATA26 PAD_MDATA27 PAD_MDQS3]
set_min_delay 1.4 -from ddr_moe_reg_7_ -to [list PAD_MDATA28 PAD_MDATA29 PAD_MDATA30 PAD_MDATA31]

#/*
# * max delays;
# */
set_max_delay 1.4 -from MEMCLK -to PAD_MDATA0
set_max_delay 1.4 -from MEMCLK -to PAD_MDATA1
set_max_delay 1.4 -from MEMCLK -to PAD_MDATA2
set_max_delay 1.4 -from MEMCLK -to PAD_MDATA3
set_max_delay 1.4 -from MEMCLK -to PAD_MDATA4
set_max_delay 1.4 -from MEMCLK -to PAD_MDATA5
set_max_delay 1.4 -from MEMCLK -to PAD_MDATA6
set_max_delay 1.4 -from MEMCLK -to PAD_MDATA7
set_max_delay 1.4 -from MEMCLK -to PAD_MDATA8
set_max_delay 1.4 -from MEMCLK -to PAD_MDATA9
set_max_delay 1.4 -from MEMCLK -to PAD_MDATA10
set_max_delay 1.4 -from MEMCLK -to PAD_MDATA11
set_max_delay 1.4 -from MEMCLK -to PAD_MDATA12
set_max_delay 1.4 -from MEMCLK -to PAD_MDATA13
set_max_delay 1.4 -from MEMCLK -to PAD_MDATA14
set_max_delay 1.4 -from MEMCLK -to PAD_MDATA15
set_max_delay 1.4 -from MEMCLK -to PAD_MDATA16
set_max_delay 1.4 -from MEMCLK -to PAD_MDATA17
set_max_delay 1.4 -from MEMCLK -to PAD_MDATA18
set_max_delay 1.4 -from MEMCLK -to PAD_MDATA19
set_max_delay 1.4 -from MEMCLK -to PAD_MDATA20
set_max_delay 1.4 -from MEMCLK -to PAD_MDATA21
set_max_delay 1.4 -from MEMCLK -to PAD_MDATA22
set_max_delay 1.4 -from MEMCLK -to PAD_MDATA23
set_max_delay 1.4 -from MEMCLK -to PAD_MDATA24
set_max_delay 1.4 -from MEMCLK -to PAD_MDATA25
set_max_delay 1.4 -from MEMCLK -to PAD_MDATA26
set_max_delay 1.4 -from MEMCLK -to PAD_MDATA27
set_max_delay 1.4 -from MEMCLK -to PAD_MDATA28
set_max_delay 1.4 -from MEMCLK -to PAD_MDATA29
set_max_delay 1.4 -from MEMCLK -to PAD_MDATA30
set_max_delay 1.4 -from MEMCLK -to PAD_MDATA31
set_max_delay 1.4 -from MEMCLK -to PAD_MDQM0
set_max_delay 1.4 -from MEMCLK -to PAD_MDQM1
set_max_delay 1.4 -from MEMCLK -to PAD_MDQM2
set_max_delay 1.4 -from MEMCLK -to PAD_MDQM3

set_max_delay 1.4 -from MEMCLK -to PAD_MDQS0
set_max_delay 1.4 -from MEMCLK -to PAD_MDQS1
set_max_delay 1.4 -from MEMCLK -to PAD_MDQS2
set_max_delay 1.4 -from MEMCLK -to PAD_MDQS3
set_max_delay 2.0 -from ddr_wr_n_reg -to PAD_MDQS0
set_max_delay 2.0 -from ddr_wr_n_reg -to PAD_MDQS1
set_max_delay 2.0 -from ddr_wr_n_reg -to PAD_MDQS2
set_max_delay 2.0 -from ddr_wr_n_reg -to PAD_MDQS3

set_max_delay 1.6 -from [list ddr_do_p_reg_0_ ddr_do_n_reg_0_] -to PAD_MDATA0
set_max_delay 1.6 -from [list ddr_do_p_reg_1_ ddr_do_n_reg_1_] -to PAD_MDATA1
set_max_delay 1.6 -from [list ddr_do_p_reg_2_ ddr_do_n_reg_2_] -to PAD_MDATA2
set_max_delay 1.6 -from [list ddr_do_p_reg_3_ ddr_do_n_reg_3_] -to PAD_MDATA3
set_max_delay 1.6 -from [list ddr_do_p_reg_4_ ddr_do_n_reg_4_] -to PAD_MDATA4
set_max_delay 1.6 -from [list ddr_do_p_reg_5_ ddr_do_n_reg_5_] -to PAD_MDATA5
set_max_delay 1.6 -from [list ddr_do_p_reg_6_ ddr_do_n_reg_6_] -to PAD_MDATA6
set_max_delay 1.6 -from [list ddr_do_p_reg_7_ ddr_do_n_reg_7_] -to PAD_MDATA7
set_max_delay 1.6 -from [list ddr_do_p_reg_8_ ddr_do_n_reg_8_] -to PAD_MDATA8
set_max_delay 1.6 -from [list ddr_do_p_reg_9_ ddr_do_n_reg_9_] -to PAD_MDATA9
set_max_delay 1.6 -from [list ddr_do_p_reg_10_ ddr_do_n_reg_10_] -to PAD_MDATA10
set_max_delay 1.6 -from [list ddr_do_p_reg_11_ ddr_do_n_reg_11_] -to PAD_MDATA11
set_max_delay 1.6 -from [list ddr_do_p_reg_12_ ddr_do_n_reg_12_] -to PAD_MDATA12
set_max_delay 1.6 -from [list ddr_do_p_reg_13_ ddr_do_n_reg_13_] -to PAD_MDATA13
set_max_delay 1.6 -from [list ddr_do_p_reg_14_ ddr_do_n_reg_14_] -to PAD_MDATA14
set_max_delay 1.6 -from [list ddr_do_p_reg_15_ ddr_do_n_reg_15_] -to PAD_MDATA15
set_max_delay 1.6 -from [list ddr_do_p_reg_16_ ddr_do_n_reg_16_] -to PAD_MDATA16
set_max_delay 1.6 -from [list ddr_do_p_reg_17_ ddr_do_n_reg_17_] -to PAD_MDATA17
set_max_delay 1.6 -from [list ddr_do_p_reg_18_ ddr_do_n_reg_18_] -to PAD_MDATA18
set_max_delay 1.6 -from [list ddr_do_p_reg_19_ ddr_do_n_reg_19_] -to PAD_MDATA19
set_max_delay 1.6 -from [list ddr_do_p_reg_20_ ddr_do_n_reg_20_] -to PAD_MDATA20
set_max_delay 1.6 -from [list ddr_do_p_reg_21_ ddr_do_n_reg_21_] -to PAD_MDATA21
set_max_delay 1.6 -from [list ddr_do_p_reg_22_ ddr_do_n_reg_22_] -to PAD_MDATA22
set_max_delay 1.6 -from [list ddr_do_p_reg_23_ ddr_do_n_reg_23_] -to PAD_MDATA23
set_max_delay 1.6 -from [list ddr_do_p_reg_24_ ddr_do_n_reg_24_] -to PAD_MDATA24
set_max_delay 1.6 -from [list ddr_do_p_reg_25_ ddr_do_n_reg_25_] -to PAD_MDATA25
set_max_delay 1.6 -from [list ddr_do_p_reg_26_ ddr_do_n_reg_26_] -to PAD_MDATA26
set_max_delay 1.6 -from [list ddr_do_p_reg_27_ ddr_do_n_reg_27_] -to PAD_MDATA27
set_max_delay 1.6 -from [list ddr_do_p_reg_28_ ddr_do_n_reg_28_] -to PAD_MDATA28
set_max_delay 1.6 -from [list ddr_do_p_reg_29_ ddr_do_n_reg_29_] -to PAD_MDATA29
set_max_delay 1.6 -from [list ddr_do_p_reg_30_ ddr_do_n_reg_30_] -to PAD_MDATA30
set_max_delay 1.6 -from [list ddr_do_p_reg_31_ ddr_do_n_reg_31_] -to PAD_MDATA31
set_max_delay 1.6 -from [list ddr_dqm_p_reg_0_ ddr_dqm_n_reg_0_] -to PAD_MDQM0
set_max_delay 1.6 -from [list ddr_dqm_p_reg_1_ ddr_dqm_n_reg_1_] -to PAD_MDQM1
set_max_delay 1.6 -from [list ddr_dqm_p_reg_2_ ddr_dqm_n_reg_2_] -to PAD_MDQM2
set_max_delay 1.6 -from [list ddr_dqm_p_reg_3_ ddr_dqm_n_reg_3_] -to PAD_MDQM3

set_max_delay 1.8 -from ddr_moe_reg_0_ -to [list PAD_MDATA0 PAD_MDATA1 PAD_MDATA2 PAD_MDATA3 PAD_MDQS0]
set_max_delay 1.8 -from ddr_moe_reg_1_ -to [list PAD_MDATA4 PAD_MDATA5 PAD_MDATA6 PAD_MDATA7]
set_max_delay 1.8 -from ddr_moe_reg_2_ -to [list PAD_MDATA8 PAD_MDATA9 PAD_MDATA10 PAD_MDATA11 PAD_MDQS1]
set_max_delay 1.8 -from ddr_moe_reg_3_ -to [list PAD_MDATA12 PAD_MDATA13 PAD_MDATA14 PAD_MDATA15]
set_max_delay 1.8 -from ddr_moe_reg_4_ -to [list PAD_MDATA16 PAD_MDATA17 PAD_MDATA18 PAD_MDATA19 PAD_MDQS2]
set_max_delay 1.8 -from ddr_moe_reg_5_ -to [list PAD_MDATA20 PAD_MDATA21 PAD_MDATA22 PAD_MDATA23]
set_max_delay 1.8 -from ddr_moe_reg_6_ -to [list PAD_MDATA24 PAD_MDATA25 PAD_MDATA26 PAD_MDATA27 PAD_MDQS3]
set_max_delay 1.8 -from ddr_moe_reg_7_ -to [list PAD_MDATA28 PAD_MDATA29 PAD_MDATA30 PAD_MDATA31]


#/*
# * ddr input data path;
# * double-date rate, synchronous to strobes;
# * remember that DDR drives strobe like a data pin;
# * delay on board centers strobes with regards to data;
# */

#/*
# * strobe clocks at bb;
# * use clock uncertainty to describe tDQSCK (data/strobe jitter);
# * clock phase is chosen to minimize ddr_mdin -> mdin paths;
# * strobe-reversal on means inverted strobe clocks;
# */
####create_clock -name BBSTB -period 4.5 -waveform [list 3.5 5.95] [list ddr_strbclk0/N01 ddr_strbclk1/N01 ddr_strbclk2/N01 ddr_strbclk3/N01 ddr_strbclk4/N01 ddr_strbclk5/N01 ddr_strbclk6/N01 ddr_strbclk7/N01]

create_clock -name BBSTB -period 4.9 -waveform [list 3.5 5.95] [get_ports PAD_MDQS*]

set_clock_uncertainty 0.5 BBSTB
set_propagated_clock [all_clocks]

#/*
# * create two virtual clocks to describe strobes;
# * external virtual flop is clocked on both edges;
# * must make opposite edges false paths;
# */
create_clock -name BBSTB_P -period 4.9 -waveform [list 3.5 5.95]
create_clock -name BBSTB_N -period 4.9 -waveform [list 5.95 8.4]
set_input_delay 2.75 -clock BBSTB_P -max [get_ports PAD_MDATA*]
set_input_delay 2.75 -clock BBSTB_N -max [get_ports PAD_MDATA*] -add_delay
set_false_path -from BBSTB_N -to [get_cells ddr_mdin_p*]
set_false_path -from BBSTB_P -to [get_cells ddr_mdin_n*]