rep.max.clock
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****************************************
Report : clock
Design : bb
Version: 2001.08-SP1
Date : Thu Mar 6 13:34:35 2003
****************************************
Attributes:
p - propagated_clock
G - Generated clock
Clock Period Waveform Attrs Sources
--------------------------------------------------------------------------------
BBSTB 4.90 {3.5 5.95} p {PAD_MDQS0 PAD_MDQS1 PAD_MDQS2 PAD_MDQS3}
BBSTB_N 4.90 {5.95 8.4} {}
BBSTB_P 4.90 {3.5 5.95} {}
DBGCLK 19.60 {0 9.8} p {dbgclk_tree/N01}
DDRCLK 4.90 {2.45 4.9} {}
JTAGCLK 39.20 {0 19.6} p {tck_tree/N01}
MEMCLK 4.90 {1.566 4.016} p {pllx2/CLKOA}
SYSCLK 9.80 {3.586 8.486} p {PAD_SYSCLK}
USBCLK 19.60 {3.949 13.749} p {PAD_USBCLKI}
VCLOCK 19.60 {4.295 14.095} p {pllv/FO}
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****************************************
Report : clock_skew
Design : bb
Version: 2001.08-SP1
Date : Thu Mar 6 13:34:35 2003
****************************************
Min Rise Min Fall Max Rise Max Fall Hold Setup
Object Delay Delay Delay Delay Uncertainty Uncertainty
--------------------------------------------------------------------------------
MEMCLK - - - - 0.20 0.20
DDRCLK 0.00 0.00 0.00 0.00 0.25 0.25
BBSTB - - - - 0.50 0.50
Min Condition Source Latency Max Condition Source Latency
--------------------------------------------------------------------------------
Object Early_r Early_f Late_r Late_f Early_r Early_f Late_r Late_f
--------------------------------------------------------------------------------
MEMCLK 2.037 2.037 2.037 2.037 2.037 2.037 2.037 2.037
From To Hold Setup
Object Object Uncertainty Uncertainty
--------------------------------------------------------------------------------
MEMCLK SYSCLK 0.20 0.20
SYSCLK MEMCLK 0.20 0.20
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