io_ddr.tcl
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################################################################
#/* ddr-I/F Timing Check Script */
# Ver 1.0 M.Honma
# Ver 1.1 H.Terai Mar.01.2003
# 1) MDATA input report is separated for each byte
# 2) Set wire_load 15 on PADs for output
################################################################
##### INPUT #####
#
# MDATA Input
#
#/* MDATA: ddr data in */
#
report_timing -max_paths 1000 -nworst 10 \
-from [get_ports {PAD_MDATA31 PAD_MDATA30 PAD_MDATA29 PAD_MDATA28 PAD_MDATA27 PAD_MDATA26 PAD_MDATA25 PAD_MDATA24}] \
-to [get_pins ddr_mdin_p*/H01 ] \
> ddr_MDATA_in_dqs3.rpt
report_timing -max_paths 1000 -nworst 10 \
-from [get_ports {PAD_MDATA31 PAD_MDATA30 PAD_MDATA29 PAD_MDATA28 PAD_MDATA27 PAD_MDATA26 PAD_MDATA25 PAD_MDATA24}] \
-to [get_pins ddr_mdin_n*/H01 ] \
>> ddr_MDATA_in_dqs3.rpt
report_timing -max_paths 1000 -nworst 10 \
-from [get_ports {PAD_MDATA23 PAD_MDATA22 PAD_MDATA21 PAD_MDATA20 PAD_MDATA19 PAD_MDATA18 PAD_MDATA17 PAD_MDATA16}] \
-to [get_pins ddr_mdin_p*/H01 ] \
> ddr_MDATA_in_dqs2.rpt
report_timing -max_paths 1000 -nworst 10 \
-from [get_ports {PAD_MDATA23 PAD_MDATA22 PAD_MDATA21 PAD_MDATA20 PAD_MDATA19 PAD_MDATA18 PAD_MDATA17 PAD_MDATA16}] \
-to [get_pins ddr_mdin_n*/H01 ] \
>> ddr_MDATA_in_dqs2.rpt
report_timing -max_paths 1000 -nworst 10 \
-from [get_ports {PAD_MDATA15 PAD_MDATA14 PAD_MDATA13 PAD_MDATA12 PAD_MDATA11 PAD_MDATA10 PAD_MDATA9 PAD_MDATA8}] \
-to [get_pins ddr_mdin_p*/H01 ] \
> ddr_MDATA_in_dqs1.rpt
report_timing -max_paths 1000 -nworst 10 \
-from [get_ports {PAD_MDATA15 PAD_MDATA14 PAD_MDATA13 PAD_MDATA12 PAD_MDATA11 PAD_MDATA10 PAD_MDATA9 PAD_MDATA8}] \
-to [get_pins ddr_mdin_n*/H01 ] \
>> ddr_MDATA_in_dqs1.rpt
report_timing -max_paths 1000 -nworst 10 \
-from [get_ports {PAD_MDATA7 PAD_MDATA6 PAD_MDATA5 PAD_MDATA4 PAD_MDATA3 PAD_MDATA2 PAD_MDATA1 PAD_MDATA0}] \
-to [get_pins ddr_mdin_p*/H01 ] \
> ddr_MDATA_in_dqs0.rpt
report_timing -max_paths 1000 -nworst 10 \
-from [get_ports {PAD_MDATA7 PAD_MDATA6 PAD_MDATA5 PAD_MDATA4 PAD_MDATA3 PAD_MDATA2 PAD_MDATA1 PAD_MDATA0}] \
-to [get_pins ddr_mdin_n*/H01 ] \
>> ddr_MDATA_in_dqs0.rpt
#
# MDQS Input
#
#/* MDQS: strobe in */
#
report_timing -max_paths 1000 -nworst 10 -from [get_ports PAD_MDQS*] \
-to [get_pins ddr_mdin_p*/H02] \
> ddr_MDQS_in.rpt
report_timing -max_paths 1000 -nworst 10 -from [get_ports PAD_MDQS*] \
-to [get_pins ddr_mdin_n*/H02] \
>> ddr_MDQS_in.rpt
set_load -wire_load 15 [get_ports { PAD_MADDR* PAD_MBANK* PAD_MCKE PAD_MCLK* PAD_MDATA* PAD_MDQM* PAD_MDQS* }]
##### OUTPUT #####
#
# MCLK Output
#
#/* ddr clock output*/
#
report_timing -max_paths 1000 -nworst 10 -from MEMCLK \
-to [get_ports PAD_MCLK*] \
> ddr_MCLK_out.rpt
#
# MADDR/CTRL Output
#
#/* ddr addr/ctrl output*/
#
report_timing -max_paths 1000 -nworst 10 -from MEMCLK \
-to [get_ports PAD_MADDR*] \
> ddr_MADDR_out.rpt
report_timing -max_paths 1000 -nworst 10 -from MEMCLK \
-to [get_ports PAD_MBANK*] \
>> ddr_MADDR_out.rpt
report_timing -max_paths 1000 -nworst 10 -from MEMCLK \
-to [get_ports {PAD_MRAS PAD_MCAS PAD_MWE PAD_MCKE}] \
>> ddr_MADDR_out.rpt
#
# MDATA Output
#
#/* MDATA: Through mux(H03) to out */
#
report_timing -max_paths 1000 -nworst 10 -from MEMCLK \
-through [get_pins ddr_domux*/H03] -to [get_ports PAD_MDATA*] \
> ddr_MDATA_MUX03_out.rpt
#
#/* MDATA: Register(DATA) to out */
#
report_timing -max_paths 1000 -nworst 10 -from MEMCLK \
-through [get_pins ddr_domux*/H01] -to [get_ports PAD_MDATA*] \
> ddr_MDATA_MUX01_out.rpt
report_timing -max_paths 1000 -nworst 10 -from MEMCLK \
-through [get_pins ddr_domux*/H02] -to [get_ports PAD_MDATA*] \
> ddr_MDATA_MUX02_out.rpt
#
#/* MDATA: Regster(OE) to out */
#
report_timing -max_paths 1000 -nworst 10 -from MEMCLK \
-through [get_pins pad_dq*/H02] -to [get_ports PAD_MDATA*] \
> ddr_MDATA_OE_out.rpt
#
# MDQS Output
#
#/* MDQS: Through mux(H03) to out */
#
report_timing -max_paths 1000 -nworst 10 -from MEMCLK \
-through [get_pins ddr_somux*/H03] -to [get_ports PAD_MDQS*] \
> ddr_MDQS_MUX03_out.rpt
#
#/* MDQS: Register to out */
#
report_timing -max_paths 1000 -nworst 10 -from MEMCLK \
-through [get_pins ddr_somux*/H01] -to [get_ports PAD_MDQS*] \
> ddr_MDQS_MUX01_out.rpt
report_timing -max_paths 1000 -nworst 10 -from MEMCLK \
-through [get_pins ddr_somux*/H02] -to [get_ports PAD_MDQS*] \
> ddr_MDQS_MUX02_out.rpt
#
#/* MDQS: Regster(OE) to out */
#
report_timing -max_paths 1000 -nworst 10 -from MEMCLK \
-through [get_pins pad_dqs*/H02] -to [get_ports PAD_MDQS*] \
> ddr_MDQS_OE_out.rpt
#
# MDQM Output
#
#/* MDQM: Through mux(H03) to out */
#
report_timing -max_paths 1000 -nworst 10 -from MEMCLK \
-through [get_pins ddr_momux*/H03] -to [get_ports PAD_MDQM*] \
> ddr_MDQM_MUX03_out.rpt
#
#/* MDQM: Register to out */
#
report_timing -max_paths 1000 -nworst 10 -from MEMCLK \
-through [get_pins ddr_momux*/H01] -to [get_ports PAD_MDQM*] \
> ddr_MDQM_MUX01_out.rpt
report_timing -max_paths 1000 -nworst 10 -from MEMCLK \
-through [get_pins ddr_domux*/H02] -to [get_ports PAD_MDQM*] \
> ddr_MDQM_MUX02_out.rpt
set_load -wire_load 0 [get_ports { PAD_MADDR* PAD_MBANK* PAD_MCKE PAD_MCLK* PAD_MDATA* PAD_MDQM* PAD_MDQS* }]
##### SCRIPT END #####