bbsoc_max.tcl 3.45 KB


set timing_disable_internal_inout_cell_paths true

set report_default_significant_digits 3

set search_path { . \
	/opc/cb12_V3.1.0/solaris/lib/CB12/common/synopsys/analog \
	/opc/cb12_V3.1.0/solaris/lib/common/synopsys/clockdriver \
	/opc/cb12_V3.1.0/solaris/lib/common/synopsys/iobuffer \
	/opc/cb12_V3.1.0/solaris/lib/common/synopsys/nec_bscan \
	/opc/cb12_V3.1.0/solaris/lib/common/synopsys/nec_scan \
	/opc/cb12_V3.1.0/solaris/lib/common/synopsys/primitive \
	/opc/cb12_V3.1.0/solaris/lib/common/synopsys/scan \
	/opc/cb12_V3.1.0/solaris/lib/common/synopsys/script \
	/opc/cb12_V3.1.0/solaris/lib/common/synopsys/special \
	/opc/cb12_V3.1.0/solaris/lib/common/synopsys/testact \
	/opc/cb12_V3.1.0/solaris/lib/common/synopsys/softmacro \
	/opc/cb12_V3.1.0/solaris/lib/common/synopsys/gating \
	/opc/cb12_V3.1.0/solaris/lib/common/synopsys/oscillator \
	/netfas5/design/bbsoc/bblib/RevA/CSR/current/lib/common/synopsys/ABD3835BM \
	/netfas5/design/bbsoc/bblib/RevA/CSR/current/lib/common/synopsys/USB1 \
	/netfas5/design/bbsoc/bblib/RevA/CSR/current/lib/common/synopsys/BINV \
	/netfas5/design/bbsoc/bblib/RevA/SRAM_ROM/current/lib/CB12/cmos_1.5V \
	/netfas5/design/bbsoc/bblib/RevA/VR4300/current \
	/netfas5/design/bbsoc/bblib/RevA/Virage_PU3/current/nvcp_nc15gfh \
	/netfas5/design/bbsoc/bblib/RevA/Virage_PU3/current/nvrm_nc15gfh_16x32 \
	/netfas5/design/bbsoc/bblib/RevA/Virage_PU3/current/nvrm_nc15gfh_64x32 \
}

set link_path { * \
\
	analog.db \
	clockdriver.db \
	iobuffer.db \
	nec_bscan.db \
	nec_scan.db \
	primitive.db \
	scan.db \
	special.db \
	testact.db \
	gating.db \
	oscillator.db \
	ABD3835BM.db \
	USB1.db \
	BINV.db \
	WBROMSMHS2048W16C5N01_STA.db \
	WBROMSMHS4096W32C5N01_STA.db \
	WBSRAMDHDWR32W32C2_STA.db \
	WBSRAMDHDWR32W72C2_STA.db \
	WBSRAMMDWQR32W8C2_STA.db \
	WBSRAMSHS128W8C3_STA.db \
	WBSRAMSHS256W16C3B8_STA.db \
	WBSRAMSHS256W41C3_STA.db \
	WBSRAMSHS256W64C3B8_STA.db \
	WBSRAMSHS4096W32C4B8_STA.db \
	WBSRAMSHS512W64C3_STA.db \
	NB4300V01_MAX_STA.db \
	nvcp_nc15gfh_MAX_STA.db \
        nvrm_nc15gfh_16x32_MAX_STA.db \
        nvrm_nc15gfh_64x32_MAX_STA.db \
}

#################################
# Read Netlist 
#################################
read_verilog ../../VCS/bb_layout.v_0313
current_design bb
link

#################################
# timing analysis at max mode. 
#################################
# Complete Sdf
read_sdf \
 -analysis_type on_chip_variation \
 -max_type sdf_max \
 -min_type sdf_max \
 ../../Verilog_SDF/bb.Universal.sdf1

#################################
# constraints 
#################################
source  ../global.tcl
source  ../pllx2.tcl
source  ../fixes.tcl

#################################
# MEMCLK uncertainty for Setup
#################################
 set_clock_uncertainty 0.2 MEMCLK
 set_clock_uncertainty 0.2 -from MEMCLK -to SYSCLK
 set_clock_uncertainty 0.2 -from SYSCLK -to MEMCLK

#################################
# report 
#################################
update_timing
report_constraint -all_violators -max_delay > rep.max.viol
report_constraint -all_violators -max_delay -verbose > rep.max.viol.verbose
report_clock        > rep.max.clock
report_clock -skew >> rep.max.clock
source  ../io_ddr.tcl
source  ../io_ddrctl_OUT.tcl
source  ../io_flash_IN.tcl
source  ../io_flash_OUT.tcl
source  ../io_gpio_IN.tcl
source  ../io_gpio_OUT.tcl
source  ../io_jchan_IN.tcl
source  ../io_jchan_OUT.tcl
source  ../io_usb_IN.tcl
source  ../io_usb_OUT.tcl
source  ../io_video_audio_OUT.tcl
source  ../io_test_IN.tcl
source  ../io_test_OUT.tcl

quit