//VERSION: 2.1.0 DATE:02/04/08 RAM TYPE: 1port Byte Write RAM
`timescale 1ps / 1ps
`celldefine
`ifdef verifault
    `suppress_faults
    `enable_portfaults
`endif
module WBSRAMSHS256W16C3B8 (
	DO15,
	DO14,
	DO13,
	DO12,
	DO11,
	DO10,
	DO9,
	DO8,
	DO7,
	DO6,
	DO5,
	DO4,
	DO3,
	DO2,
	DO1,
	DO0,
	DI15,
	DI14,
	DI13,
	DI12,
	DI11,
	DI10,
	DI9,
	DI8,
	DI7,
	DI6,
	DI5,
	DI4,
	DI3,
	DI2,
	DI1,
	DI0,
	A7,
	A6,
	A5,
	A4,
	A3,
	A2,
	A1,
	A0,
	WEB1,
	WEB0,
	CSB,
	BE,
	TBE,
	TEST,
	BUB
	);

    input DI0 ;
    input DI1 ;
    input DI2 ;
    input DI3 ;
    input DI4 ;
    input DI5 ;
    input DI6 ;
    input DI7 ;
    input DI8 ;
    input DI9 ;
    input DI10 ;
    input DI11 ;
    input DI12 ;
    input DI13 ;
    input DI14 ;
    input DI15 ;
    input A0 ;
    input A1 ;
    input A2 ;
    input A3 ;
    input A4 ;
    input A5 ;
    input A6 ;
    input A7 ;
    input WEB1 ;
    input WEB0 ;
    input CSB ;
    input BE ;
    input TBE ;
    input TEST ;
    input BUB ;
    output DO0 ;
    output DO1 ;
    output DO2 ;
    output DO3 ;
    output DO4 ;
    output DO5 ;
    output DO6 ;
    output DO7 ;
    output DO8 ;
    output DO9 ;
    output DO10 ;
    output DO11 ;
    output DO12 ;
    output DO13 ;
    output DO14 ;
    output DO15 ;

    parameter BIT=16;
    parameter WORD=256;
    parameter ADD_BIT=8;
    parameter tOH= 358;  // DO Hold

`ifdef  NEC_RTL_SIM
   parameter  tACC_r = 1353;  // Dummy value in Read mode
   parameter  tACC_w = 1004;  // Dummy value in Read mode
`endif  // NEC_RTL_SIM

	wire[BIT-1:0] DI;
	wire[ADD_BIT-1:0] A;
	wire[BIT/8-1:0] WEB;

/* -------------------------- */
reg [BIT-1:0] DO;
reg [BIT-1:0] tmp_DO;

reg [ADD_BIT-1:0] address;
reg csb, pre_BE,pre_TBE;

parameter all_X={BIT{1'bx}};

reg[BIT-1:0] memory[0:WORD-1];

// address "X" 
reg[ADD_BIT-1:0] x_add_num[0:ADD_BIT];
integer i,x_count;

   reg [BIT-1:0] tmp_data,tmp_dout,old_DO;
   reg [BIT-1:0] data;
   integer 	 j;
   reg [BIT/8-1:0] webchk;

/* -------------------------- */

`ifdef  NEC_RTL_SIM
    initial begin
      PrintRTLMsg;
    end
`endif

	// ------------------------------------- specify check flg
	wire normal_mode;
	wire test_mode;

`ifdef  NEC_RTL_SIM
`else

	reg notifier_w;
	reg notifier_a;
	reg notifier_wr;
	reg notifier_web0;
	reg notifier_web1;
        reg notifier_period;

`endif

	// ------------------------------------- dummy buffer
    buf ( _DI0, DI0 );
    buf ( _DI1, DI1 );
    buf ( _DI2, DI2 );
    buf ( _DI3, DI3 );
    buf ( _DI4, DI4 );
    buf ( _DI5, DI5 );
    buf ( _DI6, DI6 );
    buf ( _DI7, DI7 );
    buf ( _DI8, DI8 );
    buf ( _DI9, DI9 );
    buf ( _DI10, DI10 );
    buf ( _DI11, DI11 );
    buf ( _DI12, DI12 );
    buf ( _DI13, DI13 );
    buf ( _DI14, DI14 );
    buf ( _DI15, DI15 );
    buf ( _A0, A0 );
    buf ( _A1, A1 );
    buf ( _A2, A2 );
    buf ( _A3, A3 );
    buf ( _A4, A4 );
    buf ( _A5, A5 );
    buf ( _A6, A6 );
    buf ( _A7, A7 );
    buf ( _WEB0, WEB0 );
    buf ( _WEB1, WEB1 );
    buf ( _CSB, CSB );
    buf ( _BE, BE );
    buf ( _TBE, TBE );
    buf ( _TEST, TEST );
    buf ( _BUB, BUB );

    buf ( DI[0], _DI0 );
    buf ( DI[1], _DI1 );
    buf ( DI[2], _DI2 );
    buf ( DI[3], _DI3 );
    buf ( DI[4], _DI4 );
    buf ( DI[5], _DI5 );
    buf ( DI[6], _DI6 );
    buf ( DI[7], _DI7 );
    buf ( DI[8], _DI8 );
    buf ( DI[9], _DI9 );
    buf ( DI[10], _DI10 );
    buf ( DI[11], _DI11 );
    buf ( DI[12], _DI12 );
    buf ( DI[13], _DI13 );
    buf ( DI[14], _DI14 );
    buf ( DI[15], _DI15 );

    buf ( A[0], _A0 );
    buf ( A[1], _A1 );
    buf ( A[2], _A2 );
    buf ( A[3], _A3 );
    buf ( A[4], _A4 );
    buf ( A[5], _A5 );
    buf ( A[6], _A6 );
    buf ( A[7], _A7 );

    buf ( WEB[0], _WEB0 );
    buf ( WEB[1], _WEB1 );

	wire [BIT-1:0] dmy_DO;
	assign dmy_DO=DO;

    nmos ( DO0, dmy_DO[0], 1'b1 );
    nmos ( DO1, dmy_DO[1], 1'b1 );
    nmos ( DO2, dmy_DO[2], 1'b1 );
    nmos ( DO3, dmy_DO[3], 1'b1 );
    nmos ( DO4, dmy_DO[4], 1'b1 );
    nmos ( DO5, dmy_DO[5], 1'b1 );
    nmos ( DO6, dmy_DO[6], 1'b1 );
    nmos ( DO7, dmy_DO[7], 1'b1 );
    nmos ( DO8, dmy_DO[8], 1'b1 );
    nmos ( DO9, dmy_DO[9], 1'b1 );
    nmos ( DO10, dmy_DO[10], 1'b1 );
    nmos ( DO11, dmy_DO[11], 1'b1 );
    nmos ( DO12, dmy_DO[12], 1'b1 );
    nmos ( DO13, dmy_DO[13], 1'b1 );
    nmos ( DO14, dmy_DO[14], 1'b1 );
    nmos ( DO15, dmy_DO[15], 1'b1 );

   and(writepin,
       _WEB0,
       _WEB1);

/* ----------------------- specify */
	assign normal_mode=((_BUB!==0) && (_TEST!==1));
	assign test_mode=((_BUB!==0) && (_TEST!==0));

`ifdef  NEC_RTL_SIM
`else

     wire _check_n1;
     wire _check_t1;
     wire _check_n2web0;
     wire _check_n2web1;
     wire _check_t2web0;
     wire _check_t2web1;
     wire _check_n3;
     wire _check_t3;
     wire _check_bubn;
     wire _check_bubt;
     wire _check_test;
     wire _check_periodn;
     wire _check_periodt;

`endif

     buf #1 (pre_csb,csb);

`ifdef  NEC_RTL_SIM
`else

     assign _check_n1=((_CSB!==1'b1) && (normal_mode==1));
     assign _check_t1=((_CSB!==1'b1) && (test_mode==1));
     assign _check_n2web0=((_CSB!==1'b1) && (_WEB0!==1'b1) && (normal_mode==1));
     assign _check_n2web1=((_CSB!==1'b1) && (_WEB1!==1'b1) && (normal_mode==1));
     assign _check_t2web0=((_CSB!==1'b1) && (_WEB0!==1'b1) && (test_mode==1));
     assign _check_t2web1=((_CSB!==1'b1) && (_WEB1!==1'b1) && (test_mode==1));
     assign _check_n3=((normal_mode==1));
     assign _check_t3=((test_mode==1));
     assign _check_bubn=((_CSB!==1'b1) && (_TEST!==1'b1));
     assign _check_bubt=((_CSB!==1'b1) && (_TEST!==1'b0));
     assign _check_test=((_CSB!==1'b1) && (_BUB!==1'b0));
     assign _check_periodn=((normal_mode==1));
     assign _check_periodt=((test_mode==1));

`endif

`ifdef  NEC_RTL_SIM
`else

    specify
        specparam DMY_SPC=1:1:1;

	$setup ( posedge DI0, posedge BE &&& _check_n2web0, DMY_SPC, notifier_w );
	$setup ( posedge DI1, posedge BE &&& _check_n2web0, DMY_SPC, notifier_w );
	$setup ( posedge DI2, posedge BE &&& _check_n2web0, DMY_SPC, notifier_w );
	$setup ( posedge DI3, posedge BE &&& _check_n2web0, DMY_SPC, notifier_w );
	$setup ( posedge DI4, posedge BE &&& _check_n2web0, DMY_SPC, notifier_w );
	$setup ( posedge DI5, posedge BE &&& _check_n2web0, DMY_SPC, notifier_w );
	$setup ( posedge DI6, posedge BE &&& _check_n2web0, DMY_SPC, notifier_w );
	$setup ( posedge DI7, posedge BE &&& _check_n2web0, DMY_SPC, notifier_w );
	$setup ( posedge DI8, posedge BE &&& _check_n2web1, DMY_SPC, notifier_w );
	$setup ( posedge DI9, posedge BE &&& _check_n2web1, DMY_SPC, notifier_w );
	$setup ( posedge DI10, posedge BE &&& _check_n2web1, DMY_SPC, notifier_w );
	$setup ( posedge DI11, posedge BE &&& _check_n2web1, DMY_SPC, notifier_w );
	$setup ( posedge DI12, posedge BE &&& _check_n2web1, DMY_SPC, notifier_w );
	$setup ( posedge DI13, posedge BE &&& _check_n2web1, DMY_SPC, notifier_w );
	$setup ( posedge DI14, posedge BE &&& _check_n2web1, DMY_SPC, notifier_w );
	$setup ( posedge DI15, posedge BE &&& _check_n2web1, DMY_SPC, notifier_w );

  	$setup ( negedge DI0, posedge BE &&& _check_n2web0, DMY_SPC, notifier_w );
  	$setup ( negedge DI1, posedge BE &&& _check_n2web0, DMY_SPC, notifier_w );
  	$setup ( negedge DI2, posedge BE &&& _check_n2web0, DMY_SPC, notifier_w );
  	$setup ( negedge DI3, posedge BE &&& _check_n2web0, DMY_SPC, notifier_w );
  	$setup ( negedge DI4, posedge BE &&& _check_n2web0, DMY_SPC, notifier_w );
  	$setup ( negedge DI5, posedge BE &&& _check_n2web0, DMY_SPC, notifier_w );
  	$setup ( negedge DI6, posedge BE &&& _check_n2web0, DMY_SPC, notifier_w );
  	$setup ( negedge DI7, posedge BE &&& _check_n2web0, DMY_SPC, notifier_w );
  	$setup ( negedge DI8, posedge BE &&& _check_n2web1, DMY_SPC, notifier_w );
  	$setup ( negedge DI9, posedge BE &&& _check_n2web1, DMY_SPC, notifier_w );
  	$setup ( negedge DI10, posedge BE &&& _check_n2web1, DMY_SPC, notifier_w );
  	$setup ( negedge DI11, posedge BE &&& _check_n2web1, DMY_SPC, notifier_w );
  	$setup ( negedge DI12, posedge BE &&& _check_n2web1, DMY_SPC, notifier_w );
  	$setup ( negedge DI13, posedge BE &&& _check_n2web1, DMY_SPC, notifier_w );
  	$setup ( negedge DI14, posedge BE &&& _check_n2web1, DMY_SPC, notifier_w );
  	$setup ( negedge DI15, posedge BE &&& _check_n2web1, DMY_SPC, notifier_w );

	$hold ( posedge BE &&& _check_n2web0, posedge DI0, DMY_SPC, notifier_w );
	$hold ( posedge BE &&& _check_n2web0, posedge DI1, DMY_SPC, notifier_w );
	$hold ( posedge BE &&& _check_n2web0, posedge DI2, DMY_SPC, notifier_w );
	$hold ( posedge BE &&& _check_n2web0, posedge DI3, DMY_SPC, notifier_w );
	$hold ( posedge BE &&& _check_n2web0, posedge DI4, DMY_SPC, notifier_w );
	$hold ( posedge BE &&& _check_n2web0, posedge DI5, DMY_SPC, notifier_w );
	$hold ( posedge BE &&& _check_n2web0, posedge DI6, DMY_SPC, notifier_w );
	$hold ( posedge BE &&& _check_n2web0, posedge DI7, DMY_SPC, notifier_w );
	$hold ( posedge BE &&& _check_n2web1, posedge DI8, DMY_SPC, notifier_w );
	$hold ( posedge BE &&& _check_n2web1, posedge DI9, DMY_SPC, notifier_w );
	$hold ( posedge BE &&& _check_n2web1, posedge DI10, DMY_SPC, notifier_w );
	$hold ( posedge BE &&& _check_n2web1, posedge DI11, DMY_SPC, notifier_w );
	$hold ( posedge BE &&& _check_n2web1, posedge DI12, DMY_SPC, notifier_w );
	$hold ( posedge BE &&& _check_n2web1, posedge DI13, DMY_SPC, notifier_w );
	$hold ( posedge BE &&& _check_n2web1, posedge DI14, DMY_SPC, notifier_w );
	$hold ( posedge BE &&& _check_n2web1, posedge DI15, DMY_SPC, notifier_w );

	$hold ( posedge BE &&& _check_n2web0, negedge DI0, DMY_SPC, notifier_w );
	$hold ( posedge BE &&& _check_n2web0, negedge DI1, DMY_SPC, notifier_w );
	$hold ( posedge BE &&& _check_n2web0, negedge DI2, DMY_SPC, notifier_w );
	$hold ( posedge BE &&& _check_n2web0, negedge DI3, DMY_SPC, notifier_w );
	$hold ( posedge BE &&& _check_n2web0, negedge DI4, DMY_SPC, notifier_w );
	$hold ( posedge BE &&& _check_n2web0, negedge DI5, DMY_SPC, notifier_w );
	$hold ( posedge BE &&& _check_n2web0, negedge DI6, DMY_SPC, notifier_w );
	$hold ( posedge BE &&& _check_n2web0, negedge DI7, DMY_SPC, notifier_w );
	$hold ( posedge BE &&& _check_n2web1, negedge DI8, DMY_SPC, notifier_w );
	$hold ( posedge BE &&& _check_n2web1, negedge DI9, DMY_SPC, notifier_w );
	$hold ( posedge BE &&& _check_n2web1, negedge DI10, DMY_SPC, notifier_w );
	$hold ( posedge BE &&& _check_n2web1, negedge DI11, DMY_SPC, notifier_w );
	$hold ( posedge BE &&& _check_n2web1, negedge DI12, DMY_SPC, notifier_w );
	$hold ( posedge BE &&& _check_n2web1, negedge DI13, DMY_SPC, notifier_w );
	$hold ( posedge BE &&& _check_n2web1, negedge DI14, DMY_SPC, notifier_w );
	$hold ( posedge BE &&& _check_n2web1, negedge DI15, DMY_SPC, notifier_w );

	$setup ( posedge DI0, posedge TBE &&& _check_t2web0, DMY_SPC, notifier_w );
	$setup ( posedge DI1, posedge TBE &&& _check_t2web0, DMY_SPC, notifier_w );
	$setup ( posedge DI2, posedge TBE &&& _check_t2web0, DMY_SPC, notifier_w );
	$setup ( posedge DI3, posedge TBE &&& _check_t2web0, DMY_SPC, notifier_w );
	$setup ( posedge DI4, posedge TBE &&& _check_t2web0, DMY_SPC, notifier_w );
	$setup ( posedge DI5, posedge TBE &&& _check_t2web0, DMY_SPC, notifier_w );
	$setup ( posedge DI6, posedge TBE &&& _check_t2web0, DMY_SPC, notifier_w );
	$setup ( posedge DI7, posedge TBE &&& _check_t2web0, DMY_SPC, notifier_w );
	$setup ( posedge DI8, posedge TBE &&& _check_t2web1, DMY_SPC, notifier_w );
	$setup ( posedge DI9, posedge TBE &&& _check_t2web1, DMY_SPC, notifier_w );
	$setup ( posedge DI10, posedge TBE &&& _check_t2web1, DMY_SPC, notifier_w );
	$setup ( posedge DI11, posedge TBE &&& _check_t2web1, DMY_SPC, notifier_w );
	$setup ( posedge DI12, posedge TBE &&& _check_t2web1, DMY_SPC, notifier_w );
	$setup ( posedge DI13, posedge TBE &&& _check_t2web1, DMY_SPC, notifier_w );
	$setup ( posedge DI14, posedge TBE &&& _check_t2web1, DMY_SPC, notifier_w );
	$setup ( posedge DI15, posedge TBE &&& _check_t2web1, DMY_SPC, notifier_w );

	$setup ( negedge DI0, posedge TBE &&& _check_t2web0, DMY_SPC, notifier_w );
	$setup ( negedge DI1, posedge TBE &&& _check_t2web0, DMY_SPC, notifier_w );
	$setup ( negedge DI2, posedge TBE &&& _check_t2web0, DMY_SPC, notifier_w );
	$setup ( negedge DI3, posedge TBE &&& _check_t2web0, DMY_SPC, notifier_w );
	$setup ( negedge DI4, posedge TBE &&& _check_t2web0, DMY_SPC, notifier_w );
	$setup ( negedge DI5, posedge TBE &&& _check_t2web0, DMY_SPC, notifier_w );
	$setup ( negedge DI6, posedge TBE &&& _check_t2web0, DMY_SPC, notifier_w );
	$setup ( negedge DI7, posedge TBE &&& _check_t2web0, DMY_SPC, notifier_w );
	$setup ( negedge DI8, posedge TBE &&& _check_t2web1, DMY_SPC, notifier_w );
	$setup ( negedge DI9, posedge TBE &&& _check_t2web1, DMY_SPC, notifier_w );
	$setup ( negedge DI10, posedge TBE &&& _check_t2web1, DMY_SPC, notifier_w );
	$setup ( negedge DI11, posedge TBE &&& _check_t2web1, DMY_SPC, notifier_w );
	$setup ( negedge DI12, posedge TBE &&& _check_t2web1, DMY_SPC, notifier_w );
	$setup ( negedge DI13, posedge TBE &&& _check_t2web1, DMY_SPC, notifier_w );
	$setup ( negedge DI14, posedge TBE &&& _check_t2web1, DMY_SPC, notifier_w );
	$setup ( negedge DI15, posedge TBE &&& _check_t2web1, DMY_SPC, notifier_w );

	$hold ( posedge TBE &&& _check_t2web0, posedge DI0, DMY_SPC, notifier_w );
	$hold ( posedge TBE &&& _check_t2web0, posedge DI1, DMY_SPC, notifier_w );
	$hold ( posedge TBE &&& _check_t2web0, posedge DI2, DMY_SPC, notifier_w );
	$hold ( posedge TBE &&& _check_t2web0, posedge DI3, DMY_SPC, notifier_w );
	$hold ( posedge TBE &&& _check_t2web0, posedge DI4, DMY_SPC, notifier_w );
	$hold ( posedge TBE &&& _check_t2web0, posedge DI5, DMY_SPC, notifier_w );
	$hold ( posedge TBE &&& _check_t2web0, posedge DI6, DMY_SPC, notifier_w );
	$hold ( posedge TBE &&& _check_t2web0, posedge DI7, DMY_SPC, notifier_w );
	$hold ( posedge TBE &&& _check_t2web1, posedge DI8, DMY_SPC, notifier_w );
	$hold ( posedge TBE &&& _check_t2web1, posedge DI9, DMY_SPC, notifier_w );
	$hold ( posedge TBE &&& _check_t2web1, posedge DI10, DMY_SPC, notifier_w );
	$hold ( posedge TBE &&& _check_t2web1, posedge DI11, DMY_SPC, notifier_w );
	$hold ( posedge TBE &&& _check_t2web1, posedge DI12, DMY_SPC, notifier_w );
	$hold ( posedge TBE &&& _check_t2web1, posedge DI13, DMY_SPC, notifier_w );
	$hold ( posedge TBE &&& _check_t2web1, posedge DI14, DMY_SPC, notifier_w );
	$hold ( posedge TBE &&& _check_t2web1, posedge DI15, DMY_SPC, notifier_w );

	$hold ( posedge TBE &&& _check_t2web0, negedge DI0, DMY_SPC, notifier_w );
	$hold ( posedge TBE &&& _check_t2web0, negedge DI1, DMY_SPC, notifier_w );
	$hold ( posedge TBE &&& _check_t2web0, negedge DI2, DMY_SPC, notifier_w );
	$hold ( posedge TBE &&& _check_t2web0, negedge DI3, DMY_SPC, notifier_w );
	$hold ( posedge TBE &&& _check_t2web0, negedge DI4, DMY_SPC, notifier_w );
	$hold ( posedge TBE &&& _check_t2web0, negedge DI5, DMY_SPC, notifier_w );
	$hold ( posedge TBE &&& _check_t2web0, negedge DI6, DMY_SPC, notifier_w );
	$hold ( posedge TBE &&& _check_t2web0, negedge DI7, DMY_SPC, notifier_w );
	$hold ( posedge TBE &&& _check_t2web1, negedge DI8, DMY_SPC, notifier_w );
	$hold ( posedge TBE &&& _check_t2web1, negedge DI9, DMY_SPC, notifier_w );
	$hold ( posedge TBE &&& _check_t2web1, negedge DI10, DMY_SPC, notifier_w );
	$hold ( posedge TBE &&& _check_t2web1, negedge DI11, DMY_SPC, notifier_w );
	$hold ( posedge TBE &&& _check_t2web1, negedge DI12, DMY_SPC, notifier_w );
	$hold ( posedge TBE &&& _check_t2web1, negedge DI13, DMY_SPC, notifier_w );
	$hold ( posedge TBE &&& _check_t2web1, negedge DI14, DMY_SPC, notifier_w );
	$hold ( posedge TBE &&& _check_t2web1, negedge DI15, DMY_SPC, notifier_w );

	$setup ( posedge A0, posedge BE &&& _check_n1, DMY_SPC, notifier_a );
	$setup ( posedge A1, posedge BE &&& _check_n1, DMY_SPC, notifier_a );
	$setup ( posedge A2, posedge BE &&& _check_n1, DMY_SPC, notifier_a );
	$setup ( posedge A3, posedge BE &&& _check_n1, DMY_SPC, notifier_a );
	$setup ( posedge A4, posedge BE &&& _check_n1, DMY_SPC, notifier_a );
	$setup ( posedge A5, posedge BE &&& _check_n1, DMY_SPC, notifier_a );
	$setup ( posedge A6, posedge BE &&& _check_n1, DMY_SPC, notifier_a );
	$setup ( posedge A7, posedge BE &&& _check_n1, DMY_SPC, notifier_a );
	$setup ( negedge A0, posedge BE &&& _check_n1, DMY_SPC, notifier_a );
	$setup ( negedge A1, posedge BE &&& _check_n1, DMY_SPC, notifier_a );
	$setup ( negedge A2, posedge BE &&& _check_n1, DMY_SPC, notifier_a );
	$setup ( negedge A3, posedge BE &&& _check_n1, DMY_SPC, notifier_a );
	$setup ( negedge A4, posedge BE &&& _check_n1, DMY_SPC, notifier_a );
	$setup ( negedge A5, posedge BE &&& _check_n1, DMY_SPC, notifier_a );
	$setup ( negedge A6, posedge BE &&& _check_n1, DMY_SPC, notifier_a );
	$setup ( negedge A7, posedge BE &&& _check_n1, DMY_SPC, notifier_a );
	$hold ( posedge BE &&& _check_n1, posedge A0, DMY_SPC, notifier_a );
	$hold ( posedge BE &&& _check_n1, posedge A1, DMY_SPC, notifier_a );
	$hold ( posedge BE &&& _check_n1, posedge A2, DMY_SPC, notifier_a );
	$hold ( posedge BE &&& _check_n1, posedge A3, DMY_SPC, notifier_a );
	$hold ( posedge BE &&& _check_n1, posedge A4, DMY_SPC, notifier_a );
	$hold ( posedge BE &&& _check_n1, posedge A5, DMY_SPC, notifier_a );
	$hold ( posedge BE &&& _check_n1, posedge A6, DMY_SPC, notifier_a );
	$hold ( posedge BE &&& _check_n1, posedge A7, DMY_SPC, notifier_a );
	$hold ( posedge BE &&& _check_n1, negedge A0, DMY_SPC, notifier_a );
	$hold ( posedge BE &&& _check_n1, negedge A1, DMY_SPC, notifier_a );
	$hold ( posedge BE &&& _check_n1, negedge A2, DMY_SPC, notifier_a );
	$hold ( posedge BE &&& _check_n1, negedge A3, DMY_SPC, notifier_a );
	$hold ( posedge BE &&& _check_n1, negedge A4, DMY_SPC, notifier_a );
	$hold ( posedge BE &&& _check_n1, negedge A5, DMY_SPC, notifier_a );
	$hold ( posedge BE &&& _check_n1, negedge A6, DMY_SPC, notifier_a );
	$hold ( posedge BE &&& _check_n1, negedge A7, DMY_SPC, notifier_a );
	$setup ( posedge A0, posedge TBE &&& _check_t1, DMY_SPC, notifier_a );
	$setup ( posedge A1, posedge TBE &&& _check_t1, DMY_SPC, notifier_a );
	$setup ( posedge A2, posedge TBE &&& _check_t1, DMY_SPC, notifier_a );
	$setup ( posedge A3, posedge TBE &&& _check_t1, DMY_SPC, notifier_a );
	$setup ( posedge A4, posedge TBE &&& _check_t1, DMY_SPC, notifier_a );
	$setup ( posedge A5, posedge TBE &&& _check_t1, DMY_SPC, notifier_a );
	$setup ( posedge A6, posedge TBE &&& _check_t1, DMY_SPC, notifier_a );
	$setup ( posedge A7, posedge TBE &&& _check_t1, DMY_SPC, notifier_a );
	$setup ( negedge A0, posedge TBE &&& _check_t1, DMY_SPC, notifier_a );
	$setup ( negedge A1, posedge TBE &&& _check_t1, DMY_SPC, notifier_a );
	$setup ( negedge A2, posedge TBE &&& _check_t1, DMY_SPC, notifier_a );
	$setup ( negedge A3, posedge TBE &&& _check_t1, DMY_SPC, notifier_a );
	$setup ( negedge A4, posedge TBE &&& _check_t1, DMY_SPC, notifier_a );
	$setup ( negedge A5, posedge TBE &&& _check_t1, DMY_SPC, notifier_a );
	$setup ( negedge A6, posedge TBE &&& _check_t1, DMY_SPC, notifier_a );
	$setup ( negedge A7, posedge TBE &&& _check_t1, DMY_SPC, notifier_a );
	$hold ( posedge TBE &&& _check_t1, posedge A0, DMY_SPC, notifier_a );
	$hold ( posedge TBE &&& _check_t1, posedge A1, DMY_SPC, notifier_a );
	$hold ( posedge TBE &&& _check_t1, posedge A2, DMY_SPC, notifier_a );
	$hold ( posedge TBE &&& _check_t1, posedge A3, DMY_SPC, notifier_a );
	$hold ( posedge TBE &&& _check_t1, posedge A4, DMY_SPC, notifier_a );
	$hold ( posedge TBE &&& _check_t1, posedge A5, DMY_SPC, notifier_a );
	$hold ( posedge TBE &&& _check_t1, posedge A6, DMY_SPC, notifier_a );
	$hold ( posedge TBE &&& _check_t1, posedge A7, DMY_SPC, notifier_a );
	$hold ( posedge TBE &&& _check_t1, negedge A0, DMY_SPC, notifier_a );
	$hold ( posedge TBE &&& _check_t1, negedge A1, DMY_SPC, notifier_a );
	$hold ( posedge TBE &&& _check_t1, negedge A2, DMY_SPC, notifier_a );
	$hold ( posedge TBE &&& _check_t1, negedge A3, DMY_SPC, notifier_a );
	$hold ( posedge TBE &&& _check_t1, negedge A4, DMY_SPC, notifier_a );
	$hold ( posedge TBE &&& _check_t1, negedge A5, DMY_SPC, notifier_a );
	$hold ( posedge TBE &&& _check_t1, negedge A6, DMY_SPC, notifier_a );
	$hold ( posedge TBE &&& _check_t1, negedge A7, DMY_SPC, notifier_a );

        $setup ( posedge WEB0, posedge BE &&& _check_n1, DMY_SPC, notifier_web0 );
        $setup ( posedge WEB1, posedge BE &&& _check_n1, DMY_SPC, notifier_web1 );
        $setup ( negedge WEB0, posedge BE &&& _check_n1, DMY_SPC, notifier_web0 );
        $setup ( negedge WEB1, posedge BE &&& _check_n1, DMY_SPC, notifier_web1 );
        $hold ( posedge BE &&& _check_n1, posedge WEB0, DMY_SPC, notifier_web0 );
        $hold ( posedge BE &&& _check_n1, posedge WEB1, DMY_SPC, notifier_web1 );
        $hold ( posedge BE &&& _check_n1, negedge WEB0, DMY_SPC, notifier_web0 );
        $hold ( posedge BE &&& _check_n1, negedge WEB1, DMY_SPC, notifier_web1 );
        $setup ( posedge WEB0, posedge TBE &&& _check_t1, DMY_SPC, notifier_web0 );
        $setup ( posedge WEB1, posedge TBE &&& _check_t1, DMY_SPC, notifier_web1 );
        $setup ( negedge WEB0, posedge TBE &&& _check_t1, DMY_SPC, notifier_web0 );
        $setup ( negedge WEB1, posedge TBE &&& _check_t1, DMY_SPC, notifier_web1 );
        $hold ( posedge TBE &&& _check_t1, posedge WEB0, DMY_SPC, notifier_web0 );
        $hold ( posedge TBE &&& _check_t1, posedge WEB1, DMY_SPC, notifier_web1 );
        $hold ( posedge TBE &&& _check_t1, negedge WEB0, DMY_SPC, notifier_web0 );
        $hold ( posedge TBE &&& _check_t1, negedge WEB1, DMY_SPC, notifier_web1 );

        $setup ( posedge CSB, posedge BE &&& _check_n3, DMY_SPC, notifier_a );
        $setup ( negedge CSB, posedge BE &&& _check_n3, DMY_SPC, notifier_a );
        $hold ( posedge BE &&& _check_n3, posedge CSB, DMY_SPC, notifier_a );
        $hold ( posedge BE &&& _check_n3, negedge CSB, DMY_SPC, notifier_a );
        $setup ( posedge CSB, posedge TBE &&& _check_t3, DMY_SPC, notifier_a );
        $setup ( negedge CSB, posedge TBE &&& _check_t3, DMY_SPC, notifier_a );
        $hold ( posedge TBE &&& _check_t3, posedge CSB, DMY_SPC, notifier_a );
        $hold ( posedge TBE &&& _check_t3, negedge CSB, DMY_SPC, notifier_a );

        $width ( posedge BE &&& _check_n1, DMY_SPC, 0, notifier_wr );
        $width ( negedge BE &&& _check_n1, DMY_SPC, 0, notifier_a );
        $width ( posedge TBE &&& _check_t1, DMY_SPC, 0, notifier_wr );
        $width ( negedge TBE &&& _check_t1, DMY_SPC, 0, notifier_a );

        $setup ( posedge BUB, posedge BE &&& _check_bubn, DMY_SPC, notifier_a );
        $setup ( negedge BUB, posedge BE &&& _check_bubn, DMY_SPC, notifier_a );
        $hold ( posedge BE &&& _check_bubn, posedge BUB, DMY_SPC, notifier_a );
        $hold ( posedge BE &&& _check_bubn, negedge BUB, DMY_SPC, notifier_a );
        $setup ( posedge BUB, negedge BE &&& _check_bubn, DMY_SPC, notifier_a );
        $setup ( negedge BUB, negedge BE &&& _check_bubn, DMY_SPC, notifier_a );
        $hold ( negedge BE &&& _check_bubn, posedge BUB, DMY_SPC, notifier_a );
        $hold ( negedge BE &&& _check_bubn, negedge BUB, DMY_SPC, notifier_a );

        $setup ( posedge TEST, posedge BE &&& _check_test, DMY_SPC, notifier_a );
        $setup ( negedge TEST, posedge BE &&& _check_test, DMY_SPC, notifier_a );
        $hold ( posedge BE &&& _check_test, posedge TEST, DMY_SPC, notifier_a );
        $hold ( posedge BE &&& _check_test, negedge TEST, DMY_SPC, notifier_a );
        $setup ( posedge TEST, negedge BE &&& _check_test, DMY_SPC, notifier_a );
        $setup ( negedge TEST, negedge BE &&& _check_test, DMY_SPC, notifier_a );
        $hold ( negedge BE &&& _check_test, posedge TEST, DMY_SPC, notifier_a );
        $hold ( negedge BE &&& _check_test, negedge TEST, DMY_SPC, notifier_a );

        $setup ( posedge BUB, posedge TBE &&& _check_bubt, DMY_SPC, notifier_a );
        $setup ( negedge BUB, posedge TBE &&& _check_bubt, DMY_SPC, notifier_a );
        $hold ( posedge TBE &&& _check_bubt, posedge BUB, DMY_SPC, notifier_a );
        $hold ( posedge TBE &&& _check_bubt, negedge BUB, DMY_SPC, notifier_a );
        $setup ( posedge BUB, negedge TBE &&& _check_bubt, DMY_SPC, notifier_a );
        $setup ( negedge BUB, negedge TBE &&& _check_bubt, DMY_SPC, notifier_a );
        $hold ( negedge TBE &&& _check_bubt, posedge BUB, DMY_SPC, notifier_a );
        $hold ( negedge TBE &&& _check_bubt, negedge BUB, DMY_SPC, notifier_a );

        $setup ( posedge TEST, posedge TBE &&& _check_test, DMY_SPC, notifier_a );
        $setup ( negedge TEST, posedge TBE &&& _check_test, DMY_SPC, notifier_a );
        $hold ( posedge TBE &&& _check_test, posedge TEST, DMY_SPC, notifier_a );
        $hold ( posedge TBE &&& _check_test, negedge TEST, DMY_SPC, notifier_a );
        $setup ( posedge TEST, negedge TBE &&& _check_test, DMY_SPC, notifier_a );
        $setup ( negedge TEST, negedge TBE &&& _check_test, DMY_SPC, notifier_a );
        $hold ( negedge TBE &&& _check_test, posedge TEST, DMY_SPC, notifier_a );
        $hold ( negedge TBE &&& _check_test, negedge TEST, DMY_SPC, notifier_a );

        $period ( posedge BE &&& _check_periodn, DMY_SPC, notifier_period );
        $period ( posedge TBE &&& _check_periodt, DMY_SPC, notifier_period );

// <-- new spec

   if (BE&&WEB0) ( BE => DO0 ) = ( DMY_SPC, DMY_SPC );
   if (BE&&WEB0) ( BE => DO1 ) = ( DMY_SPC, DMY_SPC );
   if (BE&&WEB0) ( BE => DO2 ) = ( DMY_SPC, DMY_SPC );
   if (BE&&WEB0) ( BE => DO3 ) = ( DMY_SPC, DMY_SPC );
   if (BE&&WEB0) ( BE => DO4 ) = ( DMY_SPC, DMY_SPC );
   if (BE&&WEB0) ( BE => DO5 ) = ( DMY_SPC, DMY_SPC );
   if (BE&&WEB0) ( BE => DO6 ) = ( DMY_SPC, DMY_SPC );
   if (BE&&WEB0) ( BE => DO7 ) = ( DMY_SPC, DMY_SPC );
   if (BE&&WEB1) ( BE => DO8 ) = ( DMY_SPC, DMY_SPC );
   if (BE&&WEB1) ( BE => DO9 ) = ( DMY_SPC, DMY_SPC );
   if (BE&&WEB1) ( BE => DO10 ) = ( DMY_SPC, DMY_SPC );
   if (BE&&WEB1) ( BE => DO11 ) = ( DMY_SPC, DMY_SPC );
   if (BE&&WEB1) ( BE => DO12 ) = ( DMY_SPC, DMY_SPC );
   if (BE&&WEB1) ( BE => DO13 ) = ( DMY_SPC, DMY_SPC );
   if (BE&&WEB1) ( BE => DO14 ) = ( DMY_SPC, DMY_SPC );
   if (BE&&WEB1) ( BE => DO15 ) = ( DMY_SPC, DMY_SPC );

   if (TBE&&WEB0) ( TBE => DO0 ) = ( DMY_SPC, DMY_SPC );
   if (TBE&&WEB0) ( TBE => DO1 ) = ( DMY_SPC, DMY_SPC );
   if (TBE&&WEB0) ( TBE => DO2 ) = ( DMY_SPC, DMY_SPC );
   if (TBE&&WEB0) ( TBE => DO3 ) = ( DMY_SPC, DMY_SPC );
   if (TBE&&WEB0) ( TBE => DO4 ) = ( DMY_SPC, DMY_SPC );
   if (TBE&&WEB0) ( TBE => DO5 ) = ( DMY_SPC, DMY_SPC );
   if (TBE&&WEB0) ( TBE => DO6 ) = ( DMY_SPC, DMY_SPC );
   if (TBE&&WEB0) ( TBE => DO7 ) = ( DMY_SPC, DMY_SPC );
   if (TBE&&WEB1) ( TBE => DO8 ) = ( DMY_SPC, DMY_SPC );
   if (TBE&&WEB1) ( TBE => DO9 ) = ( DMY_SPC, DMY_SPC );
   if (TBE&&WEB1) ( TBE => DO10 ) = ( DMY_SPC, DMY_SPC );
   if (TBE&&WEB1) ( TBE => DO11 ) = ( DMY_SPC, DMY_SPC );
   if (TBE&&WEB1) ( TBE => DO12 ) = ( DMY_SPC, DMY_SPC );
   if (TBE&&WEB1) ( TBE => DO13 ) = ( DMY_SPC, DMY_SPC );
   if (TBE&&WEB1) ( TBE => DO14 ) = ( DMY_SPC, DMY_SPC );
   if (TBE&&WEB1) ( TBE => DO15 ) = ( DMY_SPC, DMY_SPC );

   if (BE&&!WEB0) ( BE => DO0 ) = ( DMY_SPC, DMY_SPC );
   if (BE&&!WEB0) ( BE => DO1 ) = ( DMY_SPC, DMY_SPC );
   if (BE&&!WEB0) ( BE => DO2 ) = ( DMY_SPC, DMY_SPC );
   if (BE&&!WEB0) ( BE => DO3 ) = ( DMY_SPC, DMY_SPC );
   if (BE&&!WEB0) ( BE => DO4 ) = ( DMY_SPC, DMY_SPC );
   if (BE&&!WEB0) ( BE => DO5 ) = ( DMY_SPC, DMY_SPC );
   if (BE&&!WEB0) ( BE => DO6 ) = ( DMY_SPC, DMY_SPC );
   if (BE&&!WEB0) ( BE => DO7 ) = ( DMY_SPC, DMY_SPC );
   if (BE&&!WEB1) ( BE => DO8 ) = ( DMY_SPC, DMY_SPC );
   if (BE&&!WEB1) ( BE => DO9 ) = ( DMY_SPC, DMY_SPC );
   if (BE&&!WEB1) ( BE => DO10 ) = ( DMY_SPC, DMY_SPC );
   if (BE&&!WEB1) ( BE => DO11 ) = ( DMY_SPC, DMY_SPC );
   if (BE&&!WEB1) ( BE => DO12 ) = ( DMY_SPC, DMY_SPC );
   if (BE&&!WEB1) ( BE => DO13 ) = ( DMY_SPC, DMY_SPC );
   if (BE&&!WEB1) ( BE => DO14 ) = ( DMY_SPC, DMY_SPC );
   if (BE&&!WEB1) ( BE => DO15 ) = ( DMY_SPC, DMY_SPC );

   if (TBE&&!WEB0) ( TBE => DO0 ) = ( DMY_SPC, DMY_SPC );
   if (TBE&&!WEB0) ( TBE => DO1 ) = ( DMY_SPC, DMY_SPC );
   if (TBE&&!WEB0) ( TBE => DO2 ) = ( DMY_SPC, DMY_SPC );
   if (TBE&&!WEB0) ( TBE => DO3 ) = ( DMY_SPC, DMY_SPC );
   if (TBE&&!WEB0) ( TBE => DO4 ) = ( DMY_SPC, DMY_SPC );
   if (TBE&&!WEB0) ( TBE => DO5 ) = ( DMY_SPC, DMY_SPC );
   if (TBE&&!WEB0) ( TBE => DO6 ) = ( DMY_SPC, DMY_SPC );
   if (TBE&&!WEB0) ( TBE => DO7 ) = ( DMY_SPC, DMY_SPC );
   if (TBE&&!WEB1) ( TBE => DO8 ) = ( DMY_SPC, DMY_SPC );
   if (TBE&&!WEB1) ( TBE => DO9 ) = ( DMY_SPC, DMY_SPC );
   if (TBE&&!WEB1) ( TBE => DO10 ) = ( DMY_SPC, DMY_SPC );
   if (TBE&&!WEB1) ( TBE => DO11 ) = ( DMY_SPC, DMY_SPC );
   if (TBE&&!WEB1) ( TBE => DO12 ) = ( DMY_SPC, DMY_SPC );
   if (TBE&&!WEB1) ( TBE => DO13 ) = ( DMY_SPC, DMY_SPC );
   if (TBE&&!WEB1) ( TBE => DO14 ) = ( DMY_SPC, DMY_SPC );
   if (TBE&&!WEB1) ( TBE => DO15 ) = ( DMY_SPC, DMY_SPC );


        // ------------ ( BUB,TEST,BUNRI => DO,TDO )= ?->"x" or "x"->? or Z
	(BUB=> DO0)=1;
	(BUB=> DO1)=1;
	(BUB=> DO2)=1;
	(BUB=> DO3)=1;
	(BUB=> DO4)=1;
	(BUB=> DO5)=1;
	(BUB=> DO6)=1;
	(BUB=> DO7)=1;
	(BUB=> DO8)=1;
	(BUB=> DO9)=1;
	(BUB=> DO10)=1;
	(BUB=> DO11)=1;
	(BUB=> DO12)=1;
	(BUB=> DO13)=1;
	(BUB=> DO14)=1;
	(BUB=> DO15)=1;
	(TEST=> DO0)=1;
	(TEST=> DO1)=1;
	(TEST=> DO2)=1;
	(TEST=> DO3)=1;
	(TEST=> DO4)=1;
	(TEST=> DO5)=1;
	(TEST=> DO6)=1;
	(TEST=> DO7)=1;
	(TEST=> DO8)=1;
	(TEST=> DO9)=1;
	(TEST=> DO10)=1;
	(TEST=> DO11)=1;
	(TEST=> DO12)=1;
	(TEST=> DO13)=1;
	(TEST=> DO14)=1;
	(TEST=> DO15)=1;
    endspecify
`endif

/* ************************** */

`ifdef  NEC_RTL_SIM
`else
// ----------------------------------------- timing error
always @ ( notifier_w ) begin
   disable FUNCT_NORMAL;
   disable FUNCT_TEST;

   address=A;
   tmp_dout=memory[address];
   for(i=0;i<BIT/8;i=i+1) begin
      if (WEB[i]!==1'b1) begin
	 tmp_data=memory[address];
	 for(j=i*8;j<(i+1)*8;j=j+1) begin
	    tmp_data[j]=1'bx;
	    tmp_DO[j]=1'bx;
	 end
	 memory[address]=tmp_data;
      end
      else begin
	 for(j=i*8;j<(i+1)*8;j=j+1) begin
	    tmp_DO[j]=tmp_dout[j];
	 end
      end
   end

   TohFunctionTimE;
end

always @ ( notifier_a ) begin
    disable FUNCT_NORMAL;
    disable FUNCT_TEST;
    address=A;
    MemWriteX;
    DO=all_X;
end

always @ ( notifier_wr ) begin
    disable FUNCT_NORMAL;
    disable FUNCT_TEST;
    address=A;
   for(i=0;i<BIT/8;i=i+1) begin
      if (WEB[i]!==1'b1) begin
	 tmp_data=memory[address];
	 for(j=i*8;j<(i+1)*8;j=j+1) begin
	    tmp_data[j]=1'bx;
	 end
	 memory[address]=tmp_data;
      end
   end

    DO=all_X;
end

always @ ( notifier_web0 ) begin
   disable FUNCT_NORMAL;
   disable FUNCT_TEST;
   address=A;
   webchk[0]=1'b1; 
   
   WebTimErrorFunct;
end

always @ ( notifier_web1 ) begin
   disable FUNCT_NORMAL;
   disable FUNCT_TEST;
   address=A;
   webchk[1]=1'b1; 
   
   WebTimErrorFunct;
end

always @ ( notifier_period ) begin
    if ( pre_csb !== 1 ) begin
       disable FUNCT_NORMAL;
       disable FUNCT_TEST;
       address=A;
       MemWriteX;
       DO=all_X;
    end
end

`endif

// ----------------------------------------- ram function

always @ ( _TEST ) begin
	   pre_BE = _BE ;
	   pre_TBE = _TBE ;
	   if ( _BUB!==1'b0 && (_BE!==1'b0 || _TBE!==1'b0)
					&& csb!==1'b1) begin
    		MemWriteX;
    		DO=all_X;
    		tmp_DO=all_X;
	   end
	   else if ( _TEST===1'bx) begin
    		DO=all_X;
    		tmp_DO=all_X;
    		if ( _CSB!==1'b1 && (_BE!==1'b0 || _TBE!==1'b0) ) begin
	  	   MemWriteX;
    	  	   tmp_DO=all_X;
          	   DO=all_X;
    		end
	   end
end

always @ ( _BUB ) begin
	   pre_BE = _BE ;
	   pre_TBE = _TBE ;
	   if ( _BUB===1'bx) begin
    		MemWriteX;
    		DO=all_X;
    		tmp_DO=all_X;
	   end
	   else if ( _TEST!==1'b1 && _BE!==1'b0 && csb!==1'b1) begin
    		MemWriteX;
    		DO=all_X;
    		tmp_DO=all_X;
	   end
	   else if ( _TEST!==1'b0 && _TBE!==1'b0 && csb!==1'b1) begin
    		MemWriteX;
    		DO=all_X;
    		tmp_DO=all_X;
	   end
	   else if ( _BUB===1'b0) begin
		DO=all_X;
	   end
end

// ---------------------------------------- _CSB change on BE/TBE=X
always @ ( _CSB ) begin
  if ((_BE===1'bx) && (_CSB!==1'b1) && (_BUB!==1'b0) && (_TEST!==1'b1)) begin
    MemWriteX;
    DO=all_X;
    tmp_DO=all_X;
  end
  if ((_TBE===1'bx) && (_CSB!==1'b1) && (_BUB!==1'b0) && (_TEST!==1'b0)) begin
    MemWriteX;
    DO=all_X;
    tmp_DO=all_X;
  end
end
// ---------------------------------------- writepin change on BE/TBE=X
always @ ( writepin ) begin
  if ((_BE===1'bx) && (_CSB!==1'b1) && (writepin!==1'b1) 
			&& (_BUB!==1'b0) && (_TEST!==1'b1)) begin
    MemWriteX;
    DO=all_X;
    tmp_DO=all_X;
  end
  if ((_TBE===1'bx) && (_CSB!==1'b1) && (writepin!==1'b1)
			&& (_BUB!==1'b0) && (_TEST!==1'b0)) begin
    MemWriteX;
    DO=all_X;
    tmp_DO=all_X;
  end
end

// ---------------------------------- function
always @ ( _BE ) begin : FUNCT_NORMAL
  if ( (_BUB===1'b1) && (_TEST===1'b0)) begin // --- normal mode
     casez ( {pre_BE,_BE} )
	2'b01 : begin // -------------- 0->1 posedge
           address=A;
           csb=_CSB;
	   ////
	   if ( _CSB===1'b0) begin
	      webchk={BIT/8{1'bx}};
	      old_DO=DO;
	      if (address > (WORD-1)) PrintWMsg_1;
	      WriteAddressXCount;
	      ///
	      if (x_count !== 0) begin
		WriteAddX;
            	DO=all_X;
		tmp_DO=all_X;
	      end
	      ///
	      else begin
		 tmp_dout=memory[address];
		 tmp_data=memory[address];
		 for(i=0;i<BIT/8;i=i+1) begin
		    ByteWriteFunction;
		 end
		 TohFunction;
	         //
	      end
	      ///
	   end
	   ////
	   else if ( _CSB===1'bx) begin
	         old_DO=DO;
	         MemWriteX;
    		 tmp_DO=all_X;
	         TohFunction;
	   end
	   ////
	end

        2'bx1 ,
        2'b?x : begin // -------------- x edge
           csb=1'bx;
	   if ( _CSB!==1'b1) begin
	         old_DO=DO;
	         MemWriteX;
    		 tmp_DO=all_X;
	         TohFunction;
	   end
	end
     endcase
	   pre_BE = _BE ;
  end
  else if ( (_BUB===1'b1) && (_TEST===1'bx)) begin // --- unkown mode
    if ( _CSB!==1'b1 && _BE!==1'b1) begin
	  pre_BE = _BE ;
          csb=1'bx;
	  MemWriteX;
    	  tmp_DO=all_X;
          DO=all_X;
    end
  end
end

// ---------------------------------- Test mode function (mode==4 only)
always @ ( _TBE ) begin : FUNCT_TEST
  if ( (_BUB===1'b1) && (_TEST===1'b1)) begin // --- normal mode
     casez ( {pre_TBE,_TBE} )
	2'b01 : begin // -------------- 0->1 posedge
           address=A;
           csb=_CSB;
	   ////
	   if ( _CSB===1'b0) begin
	      webchk={BIT/8{1'bx}};
	      old_DO=DO;
	      if (address > (WORD-1)) PrintWMsg_1;
	      WriteAddressXCount;
	      ///
	      if (x_count !== 0) begin
		WriteAddX;
		tmp_DO=all_X;
            	DO=all_X;
	      end
	      ///
	      else begin
		 tmp_dout=memory[address];
		 tmp_data=memory[address];
		 for(i=0;i<BIT/8;i=i+1) begin
		    ByteWriteFunction;
		 end
		 TohFunction;
	         //
	      end
	      ///
	   end
	   ////
	   else if ( _CSB===1'bx) begin
	         old_DO=DO;
	         MemWriteX;
    		 tmp_DO=all_X;
		 TohFunction;
	   end
	   ////
	end

        2'bx1 ,
        2'b?x : begin // -------------- x edge
           csb=1'bx;
           //#1 csb_tim=1'bx;
	   if ( _CSB!==1'b1) begin
	         old_DO=DO;
	         MemWriteX;
    		 tmp_DO=all_X;
		 TohFunction;
	   end
	end
     endcase
	   pre_TBE = _TBE ;
  end
  else if ( (_BUB===1'b1) && (_TEST===1'bx)) begin // --- unkown mode
    if ( _CSB!==1'b1 && _TBE!==1'b1) begin
	  pre_TBE = _TBE ;
          csb=1'bx;
	  MemWriteX;
    	  tmp_DO=all_X;
          DO=all_X;
    end
  end

end

// ---------------------------------- Test mode function (mode==4 only)

/* ----------------------------------- "x" conunt task */
task WriteAddressXCount;
begin
    x_count=0;                              // write address "x" count
    for (i=0;i<ADD_BIT;i=i+1) begin
        if (address[i]===1'bx) begin
            x_add_num[x_count]=i;
            x_count=x_count+1;
        end
    end
end
endtask

/* ----------------------------------- find address & write task */
task WriteAddX;

reg[ADD_BIT-1:0] new_address;
reg[ADD_BIT-1:0] b_count,num_count;
integer j,k,m;

begin
    new_address=address;
    b_count=(2<<(x_count-1))-1;
    num_count={ADD_BIT{1'b0}};
    for (j=0;j<=b_count;j=j+1) begin
        for (k=0;k<x_count;k=k+1) begin
            new_address[x_add_num[k]] = num_count[k];
            memory[new_address]=all_X;
        end
        num_count=num_count+1;
    end
end
endtask

/* ------------ write x in all address */
task MemWriteX;
integer i;
begin
  for(i=0;i<WORD;i=i+1) memory[i]=all_X;
end
endtask

/* ------------ access invalid address warning message */
task PrintWMsg_1;
begin
	$display( $time,,"%m #### You are accessing the invalid address.\n");
end
endtask

/* ------------ byte write function for WEB timing error*/
   task WebTimErrorFunct;
      //input [ADD_BIT-1:0] address;
      begin
	 tmp_dout=memory[address];
	 tmp_data=memory[address];
	 for(i=0;i<BIT/8;i=i+1) begin
	    if (1'b1==webchk[i]) begin
	       for(j=i*8;j<(i+1)*8;j=j+1) begin
		  tmp_data[j]=1'bx;
		  tmp_DO[j]=1'bx;
	       end
	       memory[address]=tmp_data;
	    end
	    else begin
	       ByteWriteFunction;
	    end
	 end

	 TohFunctionTimE;
      end
   endtask

/* ------------ byte write function */
   task ByteWriteFunction;
      begin
	 if (WEB[i]===1'b0) begin
	    data = DI;
	    for(j=i*8;j<(i+1)*8;j=j+1) begin
	       tmp_data[j]=data[j];
	       tmp_DO[j]=data[j];
	    end
	    memory[address]=tmp_data;
	 end
	 else if (WEB[i]===1'b1) begin
	    for(j=i*8;j<(i+1)*8;j=j+1) begin
	       tmp_DO[j]=tmp_dout[j];
	    end
	 end
	 else begin
	    for(j=i*8;j<(i+1)*8;j=j+1) begin
	       tmp_data[j]=1'bx;
	       tmp_DO[j]=1'bx;
	    end
	    memory[address]=tmp_data;
	 end
      end
   endtask

/* ------------ tOH function */
   task TohFunction;
      begin
	 if (DO===tmp_DO) begin
	    DO=tmp_DO;
	 end
	 else begin

`ifdef  NEC_RTL_SIM
	    #(tACC_r)  DO = tmp_DO;
`else
                     if (DO===all_X) begin
                       DO=tmp_DO;
                     end
                     else begin
			DO={BIT{1'bx}};
			#1;
			if (DO===all_X) begin
			   DO=tmp_DO;
			end
		     end
`endif  // NEC_RTL_SIM
	 end
      end
   endtask
   
   task TohFunctionTimE;
      begin
	 if (old_DO===tmp_DO) begin
	    DO=tmp_DO;
	 end
	 else begin
	    if (old_DO===all_X) begin
	       DO=tmp_DO;
	    end
	    else begin
	       DO={BIT{1'bx}};
	       #1;
	       if (DO===all_X) begin
		  DO=tmp_DO;
	       end
	    end
	 end
      end
   endtask
/* ************************** */
`ifdef  NEC_RTL_SIM
task  PrintRTLMsg;
begin
        $display("===============================================");
        $display("Pure Behavior Function Mode : WBSRAMSHS256W16C3B8");
        $display("Instance       : %m");
        $display("Abstract Delay :");
        $display("   tACC        : %d",tACC_r);
        $display("===============================================");
end
endtask
`endif

endmodule
`ifdef verifault
    `nosuppress_faults
    `disable_portfaults
`endif
`endcelldefine