flash_mon.v
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// flash_mon.v v1 Frank Berndt
// pi nand flash bus monitor;
// :set tabstop=4
module flash_mon (
sysclk, reset_l,
db, ce, ale, cle, re, we, wp, ryby,
);
input sysclk; // system clock;
input reset_l; // system reset;
input [7:0] db; // data bus;
input ce; // chip enable;
input ale; // address latch enable;
input cle; // command latch enable;
input re; // read eanble;
input we; // write eanble;
input wp; // write protect;
input ryby; // ready/busy;
// flash assertions;
// ce should never be x or z;
wire xce; // gated chip select;
assign xce = reset_l & ~ce;
always @(xce)
begin
if((xce === 'bx) | (xce === 'bz))
$display("ERROR: %t: %M: ce %b", $time, ce);
end
// while ce is active, cle and ale should not be x or z;
// cle and ale should never be active simultaneously;
always @(xce or cle or ale)
begin
if(xce & (cle === 'bx) | (cle === 'bz))
$display("ERROR: %t: %M: cle %b", $time, cle);
if(xce & (ale === 'bx) | (ale === 'bz))
$display("ERROR: %t: %M: ale %b", $time, ale);
if(xce & (cle === 1) & (ale === 1))
$display("ERROR: %t: %M: cle %b and ale %b active", $time, cle, ale);
end
// while ce is active, we and re should not be x or z;
// we and re should never be active simultaneously;
always @(we or re)
begin
if(xce & (we === 'bx) | (we === 'bz))
$display("ERROR: %t: %M: we %b", $time, we);
if(xce & (re === 'bx) | (re === 'bz))
$display("ERROR: %t: %M: re %b", $time, re);
if(xce & (we === 0) & (re === 0))
$display("ERROR: %t: %M: we %b and re %b active", $time, we, re);
end
// re should not be active with cle or ale;
always @(xce or cle or ale or re)
begin
if(xce & (re === 0) & (cle | ale))
$display("ERROR: %t: %M: re %b during cle %b ale %b phase", $time, re, cle, ale);
end
// monitor actions;
reg [7:0] cmd; // command byte;
integer naph; // # of address phases;
integer ndph; // # of data phases;
reg wrdy; // ready pulse seen;
always @(posedge we or posedge re)
begin
if(xce & (cle === 1)) begin
cmd = db;
naph = 0;
ndph = 0;
wrdy = 0;
end else if(xce & (ale === 1))
naph = naph + 1;
else
ndph = ndph + 1;
end
always @(posedge ryby)
begin
wrdy = 1;
end
endmodule