io_mon.v
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// io_mon.v v1 Frank Berndt
// pi io bus monitor;
// :set tabstop=4
module io_mon (
reset_l,
io_rst, io_ad, io_ale, io_cs, io_ior, io_iow, io_dmarq, io_dmack, io_intr,
fl_ce, fl_ale, fl_cle, fl_re, fl_we, fl_wp, fl_ryby, fl_md,
);
input reset_l; // system reset;
// io bus;
input io_rst; // io reset;
input [15:0] io_ad; // io ad bus;
input io_ale; // address latch enable;
input [3:0] io_cs; // chip selects;
input io_ior; // read pulse;
input io_iow; // write pulse;
input io_dmarq; // dma request;
input io_dmack; // dma acknowledge;
input io_intr; // io interrupt;
// nand flash controls;
input [3:0] fl_ce; // chip enables;
input fl_ale; // address latch enable;
input fl_cle; // command latch enable;
input fl_re; // read eanble;
input fl_we; // write eanble;
input fl_wp; // write protect;
input fl_ryby; // ready/busy;
input fl_md; // module detect;
// flash assertions;
// only one flash chip select can be active at a time;
always @(reset_l or fl_ce)
begin
casex({reset_l, fl_ce})
5'b0xxxx, // reset active;
5'b11111, // all deasserted;
5'b11110,
5'b11101,
5'b11011,
5'b10111: ; // above are ok;
default :
$display("ERROR: %t: %M: multiple flash ce, fl_ce %b", $time, fl_ce);
endcase
end
// instantiate flash monitors;
flash_mon fl_mon0 (
.reset_l(reset_l),
.db(io_ad[15:8]),
.ce(fl_ce[0]),
.cle(fl_cle),
.ale(fl_ale),
.we(fl_we),
.re(fl_re),
.wp(fl_wp),
.ryby(fl_ryby)
);
flash_mon fl_mon1 (
.reset_l(reset_l),
.db(io_ad[15:8]),
.ce(fl_ce[1]),
.cle(fl_cle),
.ale(fl_ale),
.we(fl_we),
.re(fl_re),
.wp(fl_wp),
.ryby(fl_ryby)
);
flash_mon fl_mon2 (
.reset_l(reset_l),
.db(io_ad[15:8]),
.ce(fl_ce[2]),
.cle(fl_cle),
.ale(fl_ale),
.we(fl_we),
.re(fl_re),
.wp(fl_wp),
.ryby(fl_ryby)
);
flash_mon fl_mon3 (
.reset_l(reset_l),
.db(io_ad[15:8]),
.ce(fl_ce[3]),
.cle(fl_cle),
.ale(fl_ale),
.we(fl_we),
.re(fl_re),
.wp(fl_wp),
.ryby(fl_ryby)
);
// report ready/busy changes;
always @(fl_ryby)
$display("%t: %M: fl_ryby %b", $time, fl_ryby);
// report removal of flash module;
always @(fl_md)
begin
if(reset_l) begin
if(fl_md === 0)
$display("%t: %M: flash module inserted", $time);
else if(fl_md === 1)
$display("%t: %M: flash module removed", $time);
else
$display("ERROR: %t: %M: fl_md %b", $time, fl_md);
end
end
// io bus assertions;
// there should never be X or Z on io_cs;
reg iorst_x; // xor of io_rst;
reg iocs_x; // xor of io_cs;
reg ioale_x; // xor of io_ale;
always @(io_rst)
begin
iorst_x = ^io_rst;
if((iorst_x === 1'bx) | (iorst_x === 1'bz))
$display("ERROR: %t: %M: io_rst %b", $time, io_rst);
end
always @(io_cs)
begin
iocs_x = ^io_cs;
if((iocs_x === 1'bx) | (iocs_x === 1'bz))
$display("ERROR: %t: %M: io_cs %b", $time, io_cs);
end
always @(io_ale)
begin
ioale_x = io_rst & ^io_ale;
if((ioale_x === 1'bx) | (ioale_x === 1'bz))
$display("ERROR: %t: %M: io_ale %b", $time, io_ale);
end
endmodule