module mspan_mon(clock);
input clock;

//
// Encode 32 bit input 
// Assumes input has only one bit set
// If low order bit is set, call that state 1 (not zero)
// this will let us index the initial 0 state (XXX could I use -1?)

function [4:0] ms_mon_encode;

    input [32:0] i;
    
    reg [4:0] z;
    
    begin
	if (i[ 0] == 1'b1)
	    z = 5'd1;
	else if (i[ 1] == 1'b1)
	    z = 5'd2;
	else if (i[ 2] == 1'b1)
	    z = 5'd3;
	else if (i[ 3] == 1'b1)
	    z = 5'd4;
	else if (i[ 4] == 1'b1)
	    z = 5'd5;
	else if (i[ 5] == 1'b1)
	    z = 5'd6;
	else if (i[ 6] == 1'b1)
	    z = 5'd7;
	else if (i[ 7] == 1'b1)
	    z = 5'd8;
	else if (i[ 8] == 1'b1)
	    z = 5'd9;
	else if (i[ 9] == 1'b1)
	    z = 5'd10;
	else if (i[10] == 1'b1)
	    z = 5'd11;
	else if (i[11] == 1'b1)
	    z = 5'd12;
	else if (i[12] == 1'b1)
	    z = 5'd13;
	else if (i[13] == 1'b1)
	    z = 5'd14;
	else if (i[14] == 1'b1)
	    z = 5'd15;
	else if (i[15] == 1'b1)
	    z = 5'd16;
	else if (i[16] == 1'b1)
	    z = 5'd17;
	else if (i[17] == 1'b1)
	    z = 5'd18;
	else if (i[18] == 1'b1)
	    z = 5'd19;
	else if (i[19] == 1'b1)
	    z = 5'd20;
	else if (i[20] == 1'b1)
	    z = 5'd21;
	else if (i[21] == 1'b1)
	    z = 5'd22;
	else if (i[22] == 1'b1)
	    z = 5'd23;
	else if (i[23] == 1'b1)
	    z = 5'd24;
	else if (i[24] == 1'b1)
	    z = 5'd25;
	else if (i[25] == 1'b1)
	    z = 5'd26;
	else if (i[26] == 1'b1)
	    z = 5'd27;
	else if (i[27] == 1'b1)
	    z = 5'd28;
	else if (i[28] == 1'b1)
	    z = 5'd29;
	else if (i[29] == 1'b1)
	    z = 5'd30;
	else if (i[30] == 1'b1)
	    z = 5'd31;
	else
	    z = 5'd0;
	    
	ms_mon_encode = z;
    end
endfunction

reg monitor_states;
reg monitor_gclk;
reg [31:0] gclock_max;
reg [31:0] gclock_cnt;

// ms_sc.state 4 possible states
reg [3:0] last_ms_sc_state;
reg [3:0] ms_sc_transitions[0:4];

// ms_si.state 4 possible states
reg [3:0] last_ms_si_state;
reg [3:0] ms_si_transitions[0:4];

// ms_sm.state 4 possible states
reg [21:0] last_ms_sm_state;
reg [21:0] ms_sm_transitions[0:22];

task ms_state_results;
    begin : vcs_sucks_1
    integer i;
    
    if (monitor_states) begin
	    $display("MSPAN State Transitions");
	    // ms_sc_transitions:
	    $display("ms_sc_transitions");
	    for (i = 0; i<= 4; i = i + 1)
		$display("%d - 0x%h", i, mspan_mon.ms_sc_transitions[i]);
    
	    // ms_si_transitions:
	    $display("ms_si_transitions");
	    for (i = 0; i<= 4; i = i + 1)
		$display("%d - 0x%h", i, mspan_mon.ms_si_transitions[i]);
    
	    // ms_sm_transitions:
	    $display("ms_sm_transitions");
	    for (i = 0; i<= 22; i = i + 1)
		$display("%d - 0x%h", i, mspan_mon.ms_sm_transitions[i]);
		
	    // ms_rp nirvana register
	    $display("ms_rp nirvana 0x%h", vsim.bb.bcp.rdp_0.ms.rp.nirvana);
	    
	    // Pointer difference
	    $display("Z ptr: 0x%h - 0x%h = 0x%h", vsim.bb.bcp.rdp_0.ms.rbzwptr, vsim.bb.bcp.rdp_0.ms.rbzrptr, vsim.bb.bcp.rdp_0.ms.rbzwptr - vsim.bb.bcp.rdp_0.ms.rbzrptr);
	    if ((vsim.bb.bcp.rdp_0.ms.rbzwptr - vsim.bb.bcp.rdp_0.ms.rbzrptr) & 3'h7)
		$display("ERROR Z ptr");
	    $display("C ptr: 0x%h - 0x%h = 0x%h", vsim.bb.bcp.rdp_0.ms.rbcwptr, vsim.bb.bcp.rdp_0.ms.rbcrptr, vsim.bb.bcp.rdp_0.ms.rbcwptr - vsim.bb.bcp.rdp_0.ms.rbcrptr);
	    if ((vsim.bb.bcp.rdp_0.ms.rbcwptr - vsim.bb.bcp.rdp_0.ms.rbcrptr) & 3'h7)
		$display("ERROR C ptr");

	    // ms_sc arc registers
	    $display("ms_sc idle_arcs 0x%h", vsim.bb.bcp.rdp_0.ms.sc.idle_arcs);
	    $display("ms_sc spanlet_arcs 0x%h", vsim.bb.bcp.rdp_0.ms.sc.spanlet_arcs);

	    // ms_si arc registers
	    $display("ms_si firstwr_arcs 0x%h", vsim.bb.bcp.rdp_0.ms.si.firstwr_arcs);
	    $display("ms_si wrz_arcs 0x%h", vsim.bb.bcp.rdp_0.ms.si.wrz_arcs);
	    $display("ms_si rdc_arcs 0x%h", vsim.bb.bcp.rdp_0.ms.si.rdc_arcs);

	    // ms_sm arc registers
	    $display("ms_sm rdctxt_arcs 0x%h", vsim.bb.bcp.rdp_0.ms.sm.rdctxt_arcs);
	    $display("ms_sm rdcdata_arcs 0x%h", vsim.bb.bcp.rdp_0.ms.sm.rdcdata_arcs);
	    $display("ms_sm rdzdata_arcs 0x%h", vsim.bb.bcp.rdp_0.ms.sm.rdzdata_arcs);
	    $display("ms_sm wrctxt_arcs 0x%h", vsim.bb.bcp.rdp_0.ms.sm.wrctxt_arcs);
	    $display("ms_sm wrcdata_arcs 0x%h", vsim.bb.bcp.rdp_0.ms.sm.wrcdata_arcs);
	    $display("ms_sm wrzdata_arcs 0x%h", vsim.bb.bcp.rdp_0.ms.sm.wrzdata_arcs);

	    $display("MSPAN State Transitions END");
	end

    end
endtask



reg [4:0] state_number;


initial begin : vcs_sucks_2
    integer i;

    monitor_states = $test$plusargs("mspan_mon");

    last_ms_sc_state = 0;
    for (i = 0; i<= 4; i = i + 1)
	ms_sc_transitions[i] = 0;
	
    last_ms_si_state = 0;
    for (i = 0; i<= 4; i = i + 1)
	ms_si_transitions[i] = 0;
	
    last_ms_sm_state = 0;
    for (i = 0; i<= 22; i = i + 1)
	ms_sm_transitions[i] = 0;
	
    if ($getnum$plusarg("gclock_mon=", gclock_max) == 1)
	begin
	$display("Simulation will end if gclock stops for %d clocks", gclock_max);
	monitor_gclk = 1;
	gclock_cnt = 0;
	end
    else
	begin
	monitor_gclk = 0;
	end

	
end

//
// Monitor the 3 state machines
//
always @(posedge clock) begin

    if (monitor_states) begin
    
	if (last_ms_sc_state != vsim.bb.bcp.rdp_0.ms.sc.state) begin
	    state_number = ms_mon_encode(last_ms_sc_state);
	    ms_sc_transitions[state_number] = (ms_sc_transitions[state_number] |
		vsim.bb.bcp.rdp_0.ms.sc.state);
	    last_ms_sc_state = vsim.bb.bcp.rdp_0.ms.sc.state;
	end
    
	if (last_ms_si_state != vsim.bb.bcp.rdp_0.ms.si.statec) begin
	    state_number = ms_mon_encode(last_ms_si_state);
	    ms_si_transitions[state_number] = (ms_si_transitions[state_number] |
		vsim.bb.bcp.rdp_0.ms.si.statec);
	    last_ms_si_state = vsim.bb.bcp.rdp_0.ms.si.statec;
	end
    
	if (last_ms_sm_state != vsim.bb.bcp.rdp_0.ms.sm.state) begin
	    state_number = ms_mon_encode(last_ms_sm_state);
	    ms_sm_transitions[state_number] = (ms_sm_transitions[state_number] |
		vsim.bb.bcp.rdp_0.ms.sm.state);
	    last_ms_sm_state = vsim.bb.bcp.rdp_0.ms.sm.state;
	end
    end
end

//
// detect gclock stalls.  If mspan has a rdram DMA REQ don't increment the counter
//
always @(negedge clock) begin
    if (monitor_gclk) begin
	if (vsim.bb.bcp.rdp_0.start_gclk == 0)
	    begin
	    if (vsim.bb.bcp.rdp_0.ms.rdramreq == 0)
		gclock_cnt = gclock_cnt + 1;
	    end
	else 
	    begin
	    gclock_cnt = 0;
	    end
	    
	if (gclock_cnt > gclock_max)
	    begin
	    $display("ERROR: gclock stopped for %d clocks.  End Simulation", gclock_max);
	    ms_state_results;
	    $finish;
	    end

    end
    
end

endmodule // ms_mon_state()