// vi_mon.v v1 Frank Berndt;
// vi monitor code;
// :set tabstop=4

`timescale 1ns/1ns

module vbus_mon;

`include "rcp.vh"
`include "define.vh"

	reg [1:256*8] vifilename;
	reg vi_snoop;		// turn vi snooping on;
	wire #1 dv_clk;

	initial
	begin
		vi_snoop = 0;
	end

	assign dv_clk = vsim.vclock;

	// dumping of the signals is controlled by test;

	always @(posedge dv_clk)
	begin
		if(vi_snoop) begin
			if($output_vi(vsim.vdata, vsim.vsync) == -1)
				$write("ERROR: %t: %M: %0s write error", $time, vifilename);
		end	
	end
endmodule