JDF F
// Created by Project Navigator ver 1.0
PROJECT dbx
DESIGN dbx Normal
DEVFAM spartan2
DEVFAMTIME 1049221000
DEVICE xc2s15
DEVICETIME 0
DEVPKG vq100
DEVPKGTIME 1049221000
DEVSPEED -6
DEVSPEEDTIME 0
FLOW XST Verilog
FLOWTIME 0
MODULE dbx.v
MODSTYLE dbx Normal
DEPASSOC dbx dbx.ucf SYSTEM
[Normal]
p_xstEquivRegRemoval=xstvlg, spartan2, Verilog.t_synthesize, 1049221506, False
xilxBitgCfg_Code=xstvlg, spartan2, Verilog.t_bitFile, 1049231881, 0xfb2003bb
xilxBitgCfg_GenOpt_BinaryFile=xstvlg, spartan2, Verilog.t_bitFile, 1049231881, True
xilxBitgStart_Clk_DriveDone=xstvlg, spartan2, Verilog.t_bitFile, 1049231713, True
[STRATEGY-LIST]
Normal=True