FDCE_1.v
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// $Header: /root/leakn64/depot/rf/hw/debug/xilinx/FDCE_1.v,v 1.1 2003/04/01 21:47:33 berndt Exp $
/*
FUNCTION : D-FLIP-FLOP with async clear and clock enable
*/
`timescale 100 ps / 10 ps
module FDCE_1 (Q, C, CE, CLR, D);
parameter INIT = 1'b0;
output Q;
reg q_out;
input C, CE, CLR, D;
tri0 GSR = glbl.GSR;
buf B1 (Q, q_out);
always @(GSR or CLR)
if (GSR)
assign q_out = INIT;
else if (CLR)
assign q_out = 0;
else
deassign q_out;
always @(negedge C)
if (CE)
q_out <= D;
specify
(posedge CLR => (Q +: 1'b0)) = (1, 1);
if (!CLR && CE)
(negedge C => (Q +: D)) = (1, 1);
endspecify
endmodule