FDCP_1.v
766 Bytes
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
// $Header: /root/leakn64/depot/rf/hw/flif/xilinx/FDCP_1.v,v 1.1 2003/08/20 23:46:46 berndt Exp $
/*
FUNCTION : D-FLIP-FLOP with async clear, async preset
*/
`timescale 100 ps / 10 ps
module FDCP_1 (Q, C, CLR, D, PRE);
parameter INIT = 1'b0;
output Q;
reg q_out;
input C, CLR, D, PRE;
tri0 GSR = glbl.GSR;
buf B1 (Q, q_out);
always @(GSR or CLR or PRE)
if (GSR)
assign q_out = INIT;
else if (CLR)
assign q_out = 0;
else if (PRE)
assign q_out = 1;
else
deassign q_out;
always @(negedge C)
q_out <= D;
specify
(posedge CLR => (Q +: 1'b0)) = (1, 1);
if (!CLR)
(posedge PRE => (Q +: 1'b1)) = (1, 1);
if (!CLR && !PRE)
(negedge C => (Q +: D)) = (1, 1);
endspecify
endmodule