/**************************************************************************
 *									  *
 *		 Copyright (C) 1996, Silicon Graphics, Inc.		  *
 *									  *
 *  These coded instructions, statements, and computer programs  contain  *
 *  unpublished  proprietary  information of Silicon Graphics, Inc., and  *
 *  are protected by Federal copyright law.  They  may  not be disclosed  *
 *  to  third  parties  or copied or duplicated in any form, in whole or  *
 *  in part, without the prior written consent of Silicon Graphics, Inc.  *
 *									  *
 **************************************************************************/
/*
 * File:        sys_misc.c
 * Creator:     scott@sgi.com
 * Create Date: Thu Feb  8 17:42:30 PST 1996
 * Purpose:     Misc tests for the Ultra 64 system, clock freq, INT 1, NMI,
 *		RDRAM
 *
 */
 

/* $BJQ99MzNr(B  $BOBED(B $B>-<y(B
 * $B%/%m%C%/8!::$r#N#T#S#C$H#P#A#L$NN>J}$KBP1~(B 
 * $B1GA|=PNOJ}<0$O(B osTvType $B$K$h$jG'<1(B 
 */

#include <ultra64.h>
#include <os_internal.h>
#include "gng.h"
#include "zaru.h"

extern void playSubway(void);
extern int  AutoVideo( int NtscMode );

#define CART_TIMER_MESSAGE	10
#define CART_INTERRUPT_MESSAGE	11
#define GNG_PRENMI_MSG		20

static OSMesg cartmsg, prenmimsg, timermsg;
static OSMesgQueue cartq, prenmiq, timerq;
static OSTimer timer;

/*
 * main.c's boot() function will read the reserved memory locations used
 * by the rdram diagnostic prior to calling osInitialize(), since this 
 * function clobbers the reserved rdram space used for this purpose.
 */
int rdramDiagErrors;
int rdramDiagStatus;
int rdramDiagSasano;
int rdramDiagExpect;
int rdramDiagReaddt;

/*
 * CLOCK FREQUENCY TEST
 *
 * The frequency test for the CPU.  Assume that the video clock is good
 * because the operator can see video on the screen.  Check that the
 * CPU frequency is within correct range.
 *
 * XXX need to change for PAL
 */
int
clocktest()
{
    OSTime starttime, endtime;	    /* in clock cycles */
    u64 retracetime;		    /* in usec */
    OSPri pri;
    OSIntMask savemask;
    u32 rcp_intr;
    unsigned char data[2];

    /* $B8!::$7$?$$1GA|=PNOJ}<0$r@_Dj(B                    */
    /* $B$3$l$r$7$J$$$H(B OS_CYCLES_TO_USEC $B%^%/%m$,8mF0:n(B */
    osViSetMode( &osViModeTable[ AutoVideo( OS_VI_NTSC_LAN1 ) ] );
    
    /* Use the video clock as a reference */
    
    pri = osGetThreadPri(NULL);
    osSetThreadPri(NULL, OS_PRIORITY_APPMAX+1);
    
    /* make sure video retrace queue is empty */
    while ( !MQ_IS_EMPTY(&retraceMessageQ) )
	(void)osRecvMesg(&retraceMessageQ, NULL, OS_MESG_BLOCK);
    
    (void)osRecvMesg(&retraceMessageQ, NULL, OS_MESG_BLOCK); /* for good luck */
    (void)osRecvMesg(&retraceMessageQ, NULL, OS_MESG_BLOCK);
    starttime = osGetTime();
    (void)osRecvMesg(&retraceMessageQ, NULL, OS_MESG_BLOCK);
    endtime = osGetTime();
    
    osSetThreadPri(NULL, pri);
    
#ifdef ALTERNATE
    savemask = osSetIntMask(OS_IM_NONE);
    
    while (!(IO_READ(MI_INTR_REG) & MI_INTR_VI))
	;
    IO_WRITE(VI_CURRENT_REG, 0);
    
    while (!(IO_READ(MI_INTR_REG) & MI_INTR_VI))
	starttime = osGetTime();;
    IO_WRITE(VI_CURRENT_REG, 0);
    
    while (!(IO_READ(MI_INTR_REG) & MI_INTR_VI))
	endtime = osGetTime();;
    IO_WRITE(VI_CURRENT_REG, 0);
    
    osSetIntMask(savemask);
#endif
    
    retracetime = OS_CYCLES_TO_USEC(endtime - starttime);
    if (ZaruReadReg2(REG_TRAPRETRACE)!=0) retracetime=0xffff;
    
    data[0]=retracetime>>8;
    data[1]=retracetime%0x100;
    ZaruWriteReg3(REG_RETRACETIME,2,data);	
    
    /* $BHo8!::J*$NA*Br(B */
    if( osTvType == PAL ){
	/* $B#P#A#L$N>l9g$N5vMFHO0O(B */
	if ( retracetime < PAL_USEC_PER_RETRACE - PAL_USEC_RANGE ||
	     retracetime > PAL_USEC_PER_RETRACE + PAL_USEC_RANGE )
	    return GNG_TEST_FAILURE;
	else
	    return GNG_TEST_SUCCESS;
    }else{
	/* $B#N#T#S#C!&#M#P#A#L$N>l9g$N5vMFHO0O(B */
	if ( retracetime < NTSC_USEC_PER_RETRACE - NTSC_USEC_RANGE ||
	     retracetime > NTSC_USEC_PER_RETRACE + NTSC_USEC_RANGE )
	    return GNG_TEST_FAILURE;
	else
	    return GNG_TEST_SUCCESS;
    }
}

/*
 * INT1 TEST
 * 
 * The INT1, also known as CARTINT test.  This test uses the special HW
 * in the GNG ROM cartridge to generate the interrupt that comes in over
 * the AD16 bus.  We read a Zaru register bit to detect whether or not the
 * interrupt was detected on the bottom connector (the interrupt is generated
 * by a write to the rom cartridge on the top connector).
 */
int
intr1test()
{
    extern s32 clearint1( void );
    u32    saveMask;
    int    retval;
    OSMesg Message;                /* $B#I#N#T3d$j9~$_<u<h$j%a%C%;!<%8(B */


    /* Be optimistic, assume success */
    retval = GNG_TEST_SUCCESS;

#ifdef _FINALROM

    osCreateMesgQueue(&cartq, &cartmsg, 1);
#ifdef __sgi__
    __osSetHWIntrRoutine(1, clearint1);
#else
    __osSetHWIntrRoutine(1, clearint1, NULL);
#endif
    osSetEventMesg(OS_EVENT_CART, &cartq, (OSMesg)CART_INTERRUPT_MESSAGE);
    
    /* fire off a half second timer.  Should receive message before then */
    osSetTimer(&timer, OS_USEC_TO_CYCLES(500000), 0, &cartq, (OSMesg)CART_TIMER_MESSAGE);
    
    /*
     * XXX any need to check INT bit in Zaru now?
     */

    /* Block all interrupts before setting the bit. */
    saveMask = __osDisableInt();
    
    /* Cause the interrupt (IO_WRITE does the PHYS_TO_K1 conversion) */
    IO_WRITE((u32)(INT1_ADDR), INT1_SET_DATA);
    
#ifdef NEEDS_WORKING_ZARU
    /* XXX Check Zaru bit to see if bottom pin detects interrupt line active */
    if (ZaruGetInt1() == 0) {
	retval = GNG_TEST_FAILURE;
    }
#endif
    
    /*
     * Enable interrupts to check board connection of interrupt to CPU.
     * The exception handler will call clearint1() to clear the HW
     * interrupt with interrupts blocked, and then send the OS_EVENT_CART
     * message to this thread.
     */
    __osRestoreInt(saveMask);

    /* now block for either the cartridge interrupt or the timer interrupt */
    osRecvMesg(&cartq, &Message, OS_MESG_BLOCK);

    if (Message == (OSMesg)CART_INTERRUPT_MESSAGE) {
	osStopTimer(&timer);	    /* retval was set to SUCCESS above */
    } else {
	retval = GNG_TEST_FAILURE;
    }

    /*
     * XXX any need to check INT bit in Zaru now?
     */

    /* clean up */
#ifdef __sgi__
    __osSetHWIntrRoutine(1, NULL);
#else
    __osSetHWIntrRoutine(1, NULL, NULL);
#endif
    
#endif
    
    /* indicate success or failure */

    if (ZaruReadReg2(REG_TRAPINT1) != 0) retval=GNG_TEST_FAILURE;

    return retval;

}

/*
 * RESET/INT2/NMI TEST
 *
 * Test for the RESET Switch. Here is what happens when RESET is pushed:
 * 
 * When the RESET switch is pushed, the hardware generates an
 * INT2 that gets turned into a PRENMI event.  GNG should set up to catch
 * the PRENMI event early.  The PRENMI event will be followed by a NMI to
 * the R4300 CPU in .5 seconds. If the RESET switch is pushed and held for
 * more than .5 seconds, the NMI will not occur until immediately after
 * the switch is released. The NMI will "reboot" the game.

 * After the NMI occurs, the game reboots.  The hardware is initialized,
 * the first Meg of the game in ROM is copied into the first Megabyte of
 * RAM after the boot address, the BSS for the boot segment is cleared and
 * the boot procedure is called.  This is exactly the same as a power on
 * reset with some minor differences.  The hardware initialization is
 * different.  On a power on reset, the caches are invalidated, after a
 * NMI the caches are flushed before they are invalidated.  The power on
 * reset also configures the RAM, while after a NMI the RAMs are left
 * alone.  The contents of memory, except for the 1 Meg that is copied in,
 * are the same as before the NMI occured.  The global variable,
 * osResetType, is set to 0 on a power up reset and to 1 on a NMI.
 *
 * The GNG test for RESET/NMI should check the following:
 * 1) INT2 occurs after prompting the operator to push the reset
 * 2) NMI occurs between .4 seconds & 2 seconds after the INT2 (If the operator
 *    holds the RESET button down for 2 seconds the test will fail)
 * 3) Check that NMI does not occur at other times
 *
 */
int
nmitest_phase1()
{
	char Message[80];

    gngstatus	*pstatus;
    
    /*
     * osAppNMIBuffer == 0x8000031c in locore rdram
     */
    pstatus = (gngstatus *)osAppNMIBuffer;

    pstatus->nmi_count = 0; /* sasano added */
    pstatus->nmi_first_timer = 0;
    pstatus->nmi_second_timer = 0;

    osCreateMesgQueue(&prenmiq, &prenmimsg, 1);
    osCreateMesgQueue(&timerq, &timermsg, 1);
    osSetEventMesg(OS_EVENT_PRENMI, &prenmiq, (OSMesg)GNG_PRENMI_MSG);

    /*
     * Play an alert noise to indicate to the user that they need to press
     * the button.
     */
    playSubway();

		sprintf(Message,"Push RESET switch");
    gng_report(Message, 0, 0, 1);

		ZaruWriteReg2(REG_RESET,ZARU_RESET); /* sasano added */

    /* now wait for prenmi message */
    osRecvMesg(&prenmiq, &prenmimsg, OS_MESG_BLOCK);
        
		sprintf(Message,"Push RESET switch\n -> Sequence1");
    gng_report(Message, 0, 0, 1);

		if (ZaruReadReg2(REG_TRAPNMI) !=0) return GNG_TEST_FAILURE;

    /* fire off a .4 second timer.  Should not receive NMI before then */
    osSetTimer(&timer, OS_USEC_TO_CYCLES(400000), 0, &timerq, (OSMesg)NULL);
    osRecvMesg(&timerq, &timermsg, OS_MESG_BLOCK);
    pstatus->nmi_first_timer = 1;
    
		sprintf(Message,"Push RESET switch\n -> Sequence2");
    gng_report(Message, 0, 0, 1);

    /* fire off a 1.6 second timer.  Should never return from recv message */
    osSetTimer(&timer, OS_USEC_TO_CYCLES(1600000), 0, &timerq, (OSMesg)NULL);
    osRecvMesg(&timerq, &timermsg, OS_MESG_BLOCK);
    pstatus->nmi_second_timer = 1;
    
		sprintf(Message,"Push RESET switch -> 3");
    gng_report(Message, 0, 0, 1);

    /* ERROR if we get here */
    return GNG_TEST_FAILURE;    
}

int
nmitest_phase2()
{
    gngstatus	*pstatus;
    
    /*
     * osAppNMIBuffer == 0x8000031c in locore rdram
     */
    pstatus = (gngstatus *)osAppNMIBuffer;

    if (pstatus->nmi_count != 1)
	return 1;
    if (pstatus->nmi_first_timer != 1)
	return 2;
    if (pstatus->nmi_second_timer != 0)
	return 3;

    return GNG_TEST_SUCCESS;
}

/* 
 * The RDRAM test is run immediately after the gng program boots.  The boot()
 * function checks a reserved word in rdram to see if the rdram test has been
 * run yet; if not, it boots a small program into dmem which runs the rdram 
 * test, then copies the gng boot segment back into rdram memory again, and 
 * jumps to it.  The second time around, the boot code figures out that the 
 * rdram test has been run, then jumps to the standard testDriver, which invokes
 * the function below to determine the results of the rdram test & gng_report
 * these results to the screen.
 *
 * We then reset the reserved word variables to zero, in case we are running
 * on a development board where the memory might not be explicitly cleared
 * by a power cycle.
 */

int
rdramTest()
{
    u8 dipSettings;
    int expectedSize;
    char message[256];
    gngstatus	*pstatus;
    u8 data[16];
    
    /*
     * osAppNMIBuffer == 0x8000031c in locore rdram
     */
    pstatus = (gngstatus *)osAppNMIBuffer;

    if (zaruexists) {
/*	dipSettings = ZaruGetDIPSwitch();*/
/*	dipSettings &= 0x3;*/
		dipSettings = ZaruReadReg2(REG_RDRAMSIZE); /* sasano added */

	switch (dipSettings) {
	    case ZARU_4MB:
		expectedSize = 0x400000;
		break;
	    case ZARU_6MB:
		expectedSize = 0x600000;
		break;
	    case ZARU_8MB:
		expectedSize = 0x800000;
		break;
	    default:
		gng_report( "RDRAM setting error.\n(0:4MB 1:6MB 2:8MB)",
                1, GNG_PASS_FAIL_BIT,1);

		/* not reached */
		return GNG_TEST_FAILURE;    
		break;
	}

  ZaruWriteReg2(REG_MEMSIZ,(int)(osMemSize>>16));	/* sasano added */
	if (expectedSize != osMemSize) {

	    sprintf(message, "RDRAM memory size 0x%x\nexpected size 0x%x\n",
		osMemSize, expectedSize);
	    gng_report(message, 1, GNG_PASS_FAIL_BIT, 1);

	    /* not reached */
	    return GNG_TEST_FAILURE;    
	}
    }

    /*
     * Clear reserved word variables in case of program restart without
     * a power cycle to clear memory.
     */
/* sasano
    pstatus->rdram_diag_status = 0;
    pstatus->rdram_diag_errors = 0;
*/

    data[ 0]=(u8)pstatus->rdram_diag_status;
    data[ 1]=(u8)pstatus->rdram_diag_errors;
    data[ 4]=(u8)(pstatus->rdram_diag_sasano>>24);
    data[ 5]=(u8)(pstatus->rdram_diag_sasano>>16);
    data[ 6]=(u8)(pstatus->rdram_diag_sasano>>8);
    data[ 7]=(u8)(pstatus->rdram_diag_sasano);
    data[ 8]=(u8)(pstatus->rdram_diag_expect>>24);
    data[ 9]=(u8)(pstatus->rdram_diag_expect>>16);
    data[10]=(u8)(pstatus->rdram_diag_expect>>8);
    data[11]=(u8)(pstatus->rdram_diag_expect);
    data[12]=(u8)(pstatus->rdram_diag_readdt>>24);
    data[13]=(u8)(pstatus->rdram_diag_readdt>>16);
    data[14]=(u8)(pstatus->rdram_diag_readdt>>8);
    data[15]=(u8)(pstatus->rdram_diag_readdt);
    ZaruWriteReg3(REG_RDRAMRESULT,16,data);

    if ( rdramDiagErrors == 0 ) {
	return GNG_TEST_SUCCESS;
    } else {
	return GNG_TEST_FAILURE;    
    }
}