emuwrite.c
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#include "cpusim.h"
#define saved_cause (*(volatile int*)PHYS_TO_K1(INTERNAL_RAM_START))
#define CNONMEM_WORD (*(vu32*)PHYS_TO_K0(PI_BUFFER_BASE_REG))
void
passed(void) {
message("test emuwrite passed\n");
DBG_JTAG_PASS("test emuwrite passed\n");
test_postamble();
}
void
failed(const char* code) {
message("test emuwrite failed (");
message(code);
message(")\n");
DBG_JTAG_FAIL(code);
test_postamble();
}
/* run from the exception handler. don't use regular regs, or stack */
/* stash away the cause register at 0xbfc40000, clear it, disable SR_IE */
void exception(void) {
//saved_cause = getcp0reg(C0_CAUSE);
//setcp0reg(C0_CAUSE, 0);
__asm__ __volatile__ ("lui\t$26,0xbfc4\n\t"
"mfc0\t$27,$13\n\t"
"sw\t$27,0($26)\n\t"
"mtc0\t$0,$13\n\t"
"mfc0\t$27,$12\n\t"
"li\t$26,-2\n\t"
"and\t$27,$26\n\t"
"mtc0\t$27,$12\n\t"
"eret");
}
int
main() {
extern void *__exception;
/* check for nmi */
if (getcp0reg(C0_SR) & SR_SR) {
if (IO_READ(MI_SEC_MODE_REG) ==
(MI_SEC_MODE_IRAM_ACCESS|MI_SEC_MODE_APP|MI_SEC_MODE_BROM_LO|MI_SEC_MODE_SECURE))
passed();
failed("7");
}
setcp0reg(C0_CONFIG, CONFIG_BE|CONFIG_NONCOHRNT);
test_preamble();
__exception = exception;
init_ddr();
saved_cause = 0;
setcp0reg(C0_SR, SR_CU0|SR_CU1|SR_BEV|SR_IMASK|SR_IE);
IO_WRITE(PI_ERROR_REG, PI_ERROR_SYS_INTR);
IO_WRITE(MI_INTR_EMASK_REG, MI_INTR_MASK_SET_PI_ERR);
/* PIO write */
IO_WRITE(PI_DOM1_ADDR1, 0xbabecafe);
IO_READ(PI_STATUS_REG); /* sleep a little */
if ((saved_cause & CAUSE_IP4) != CAUSE_IP4 ||
(IO_READ(MI_EINTR_REG) & MI_INTR_PI_ERR) !=
MI_INTR_PI_ERR)
failed("3");
if ((IO_READ(PI_ERROR_REG) & PI_ERROR_WRITE_TRAP) != PI_ERROR_WRITE_TRAP ) failed("4");
if (IO_READ(PI_EDATA_REG) != 0xbabecafe) failed("5");
if (IO_READ(PI_CART_ADDR_REG) != PI_DOM1_ADDR1) failed("6");
IO_WRITE(PI_IDE3_BASE_REG, IO_READ(PI_STATUS_REG));
/* clear error */
IO_WRITE(PI_ERROR_REG, PI_ERROR_SYS_INTR);
saved_cause = 0;
setcp0reg(C0_SR, SR_CU0|SR_CU1|SR_BEV|SR_IMASK|SR_IE);
/* DMA write */
IO_WRITE(PI_DRAM_ADDR_REG, K0_TO_PHYS(K0BASE));
IO_WRITE(PI_CART_ADDR_REG, PI_DOM1_ADDR1+16);
IO_WRITE(PI_RD_LEN_REG, 1024-1);
IO_READ(PI_STATUS_REG); /* sleep a little */
if ((saved_cause & CAUSE_IP4) != CAUSE_IP4 ||
(IO_READ(MI_EINTR_REG) & MI_INTR_PI_ERR) !=
MI_INTR_PI_ERR)
failed("7");
if ((IO_READ(PI_ERROR_REG) & PI_ERROR_WRITE_TRAP) != PI_ERROR_WRITE_TRAP ) failed("8");
if ((IO_READ(PI_STATUS_REG) & PI_STATUS_DMA_BUSY) != PI_STATUS_DMA_BUSY) failed("9");
if (IO_READ(PI_CART_ADDR_REG) != PI_DOM1_ADDR1+16) failed("10");
if (IO_READ(PI_RD_LEN_REG) != 1024-1) failed("11");
IO_WRITE(PI_STATUS_REG, PI_STATUS_DMA_BUSY);
if ((IO_READ(PI_STATUS_REG) & PI_STATUS_DMA_BUSY) != 0) failed("12");
passed();
return 0;
}