#include <sys/types.h>
#ifdef __sgi__
#include <sys/sbd.h>
#endif
#include <sys/stat.h>
#include <sys/mman.h>
#ifdef __sgi__
#include <sys/sema.h>
#endif
#include <netinet/in.h>

#include <errno.h>
#include <stdio.h>
#include <fcntl.h>
#include <stdlib.h>
#include <getopt.h>
#include <math.h>

#include "diag.h"
#include "dbg_comm.h"

#define TEST_RI_REG 1
#define TEST_BIT_MEMORY 3
#define TEST_BIT_EXTEND 4
#define TEST_INTERLEAVE_MEMORY 5
#define TEST_INTERLEAVE_EXTEND 6
#define TEST_RANDOM_MEMORY 7
#define TEST_RANDOM_EXTEND 8
#define TEST_RANDOM 100

#define BYTES_PER_WORD 8
#define WORDS_PER_ROW 256
#define ROWS_PER_BANK 512
#define BANKS_PER_RDRAM 2
#define RDRAMS_PER_MEMORY 2

#define WORD_SIZE BYTES_PER_WORD
#define ROW_SIZE (WORDS_PER_ROW * WORD_SIZE)
#define BANK_SIZE (ROWS_PER_BANK * ROW_SIZE)
#define RDRAM_SIZE (BANKS_PER_RDRAM * BANK_SIZE)
#define MEMORY_SIZE (RDRAMS_PER_MEMORY * RDRAM_SIZE)

#define DEFAULT_RANDOM_CYCLES 200
#define DEFAULT_RDRAM_START_ADDRESS (0x200000 - 0x10000)
/* #define DEFAULT_RDRAM_END_ADDRESS MEMORY_SIZE */
#define DEFAULT_RDRAM_END_ADDRESS (0x200000 + 0x10000)
#define RANDOM_BURST_SIZE 100

static int test_ri_reg(void);
static int test_bit_memory(void);
static int test_bit_extend(void);
static int test_interleave_memory(void);
static int test_interleave_extend(void);
static int test_random_memory(void);
static int test_random_extend(void);
static int test_random_burst(void);

static int init(void);
static int run(TEST_REF *test_ref);

int bit_test(unsigned int start_address, unsigned int end_address,
	     unsigned int write_data);

int interleave_test(unsigned int start_address, unsigned int end_address,
		    unsigned int pattern_0, unsigned int pattern_1,
		    unsigned int block_size);

int random_test(unsigned int start_address, unsigned int end_address,
		unsigned int mask);


/* IDE test interface */
static TEST_REF Test_Refs[] = {
  {"RI reg test", TEST_RI_REG, test_ri_reg},
  {"bit memory RW test", TEST_BIT_MEMORY, test_bit_memory},
  {"bit extend RW test", TEST_BIT_EXTEND, test_bit_extend},
  {"interleave memory RW test", TEST_INTERLEAVE_MEMORY, test_interleave_memory},
  {"interleave extend RW test", TEST_INTERLEAVE_EXTEND, test_interleave_extend},
  {"random word memory RW test", TEST_RANDOM_MEMORY, test_random_memory},
  {"random word extend RW test", TEST_RANDOM_EXTEND, test_random_extend},
  {"random RW test", TEST_RANDOM, test_random_burst},
  {"", 0, 0}
};

static int Initialize;
static int Failed;
static int Register_1_Valid, Register_1;
static int Register_2_Valid, Register_2;
static int Register_3_Valid, Register_3;


void
rdram(void)
{
  int c;
  extern char *optarg;
  extern int optind;

  Initialize = 1;
  Failed = 0;
  Register_1_Valid = 0;
  Register_2_Valid = 0;
  Register_3_Valid = 0;
  commtype = 3;

  while ((c = getopt(pGlobalComm->argc, pGlobalComm->argv, "ht:i1:2:3:I")) != EOF) {
    switch(c) {

    case 'h':
      dgListSubTests(Test_Refs);
      return;
      
    case 't':
      pGlobalComm->entryNum = -atoi(optarg);
      break;
      
    case 'I':
      Initialize = 0;
      break;

    case '1':
      Register_1_Valid = 1;
      Register_1 = atoi(optarg);
      break;

    case '2':
      Register_2_Valid = 1;
      Register_2 = atoi(optarg);
      break;

    case '3':
      Register_3_Valid = 1;
      Register_3 = atoi(optarg);
      break;

    default:
      return;
    }
  }

  diaginit(Test_Refs, init, run);

  if (Failed) {
    errlog(INFO, "test %s FAILED", ideTestName);
  } else {
    errlog(INFO, "test %s PASSED", ideTestName);
  }
  commtype = 5;
  return;
}


static int
init(void)
{
  errlog(INFO, "starting test %s", ideTestName);
  return 0;
}


static int
run(TEST_REF *test_ref)
{
  int rc;
  int error_count;

  errlog(INFO, "--- starting subtest %s (%d)", test_ref->name, test_ref->num);

  /* reset the target system, if necessary */
  if (Initialize) {
    errlog(DEBUG, "initializing target");
    dgInitComm();
    dgInitRdram();
  }

  if (error_count = test_ref->fnc()) {
    Failed = 1;
    errlog(INFO, "--- subtest %s FAILED, %d failures",
	   test_ref->name, error_count);
  } else {
    errlog(INFO, "--- subtest %s PASSED", test_ref->name);
  }
  return 0;
}


int
test_ri_reg(void)
{
  int error_count = 0;

  if (commtype == DG_TINYMON_RDRAM) {
     return 0;
     }

  if (dgTestReg(0x04700000, 0x00000000, 0x00000000)) error_count++;
  if (dgTestReg(0x04700000, 0xffffffff, 0x0000000f)) error_count++;
  if (dgTestReg(0x04700004, 0x00000000, 0x00000000)) error_count++;
  if (dgTestReg(0x04700004, 0xffffffff, 0x0000007f)) error_count++;
  if (dgTestReg(0x0470000c, 0x00000000, 0x00000000)) error_count++;
  if (dgTestReg(0x0470000c, 0xffffffff, 0x000000ff)) error_count++;
  /* if (dgTestReg(0x04700010, 0x00000000, 0x00000000)) error_count++; */
  /* if (dgTestReg(0x04700010, 0xffffffff, 0x0007ffff)) error_count++; */
  if (dgTestReg(0x04700014, 0x00000000, 0x00000000)) error_count++;
  if (dgTestReg(0x04700014, 0xffffffff, 0x0000000f)) error_count++;
  if (dgTestReg(0x04700018, 0x00000000, 0x00000000)) error_count++;
  if (dgTestReg(0x04700018, 0xffffffff, 0x00000000)) error_count++;
  return error_count;
}


int
test_bit_memory(void)
{
  unsigned int start_address, end_address;
  int error_count = 0;

  /* enable video to create more stress */
  dgEnableVideo(0x100000, 13);

  start_address = Register_1_Valid ? Register_1 : DEFAULT_RDRAM_START_ADDRESS;
  end_address = Register_2_Valid ? Register_2 : DEFAULT_RDRAM_END_ADDRESS;

  if (Register_3_Valid) {
    error_count
      += bit_test(start_address, end_address, Register_3);
  } else {
    error_count
      += bit_test(start_address, end_address, 0x00000000);
    error_count
      += bit_test(start_address, end_address, 0xffffffff);

    error_count
      += bit_test(start_address, end_address, 0x55555555);
    error_count
      += bit_test(start_address, end_address, 0x33333333);
    error_count
      += bit_test(start_address, end_address, 0x0f0f0f0f);
    error_count
      += bit_test(start_address, end_address, 0x00ff00ff);
    error_count
      += bit_test(start_address, end_address, 0x0000ffff);

    error_count
      += bit_test(start_address, end_address, 0xaaaaaaaa);
    error_count
      += bit_test(start_address, end_address, 0xcccccccc);
    error_count
      += bit_test(start_address, end_address, 0xf0f0f0f0);
    error_count
      += bit_test(start_address, end_address, 0xff00ff00);
    error_count
      += bit_test(start_address, end_address, 0xffff0000);
  }
  return error_count;
}


int
test_bit_extend(void) {
  unsigned int start_address, end_address;
  int error_count = 0;

  if (commtype == DG_TINYMON_RDRAM) {
     return 0;
     }

  /* enable video to create more stress */
  dgEnableVideo(0x100000, 13);

  /* set ebus test mode */
  dgWriteWord(0x04300000, 0x00000400);

  start_address = Register_1_Valid ? Register_1 : DEFAULT_RDRAM_START_ADDRESS;
  end_address = Register_2_Valid ? Register_2 : DEFAULT_RDRAM_END_ADDRESS;

  if (Register_3_Valid) {
    error_count
      += bit_test(start_address, end_address, Register_3);
  } else {
    error_count
      += bit_test(start_address, end_address, 0x0);
    error_count
      += bit_test(start_address, end_address, 0xf);
    error_count
      += bit_test(start_address, end_address, 0x5);
    error_count
      += bit_test(start_address, end_address, 0x3);
    error_count
      += bit_test(start_address, end_address, 0xa);
    error_count
      += bit_test(start_address, end_address, 0xc);
  }
  return error_count;
}


int
test_interleave_memory(void)
{
  unsigned int start_address, end_address;
  int error_count = 0;

  /* enable video to create more stress */
  dgEnableVideo(0x100000, 13);

  start_address = Register_1_Valid ? Register_1 : DEFAULT_RDRAM_START_ADDRESS;
  end_address = Register_2_Valid ? Register_2 : DEFAULT_RDRAM_END_ADDRESS;

  error_count
    += interleave_test(start_address, end_address, 0x00000000, 0xffffffff, 4);
  error_count
    += interleave_test(start_address, end_address, 0xffffffff, 0x00000000, 4);
  error_count
    += interleave_test(start_address, end_address, 0x00000000, 0xffffffff, 8);
  error_count
    += interleave_test(start_address, end_address, 0xffffffff, 0x00000000, 8);

  return error_count;
}


int
test_interleave_extend(void)
{
  unsigned int start_address, end_address;
  int error_count = 0;

  if (commtype == DG_TINYMON_RDRAM) {
     return 0;
     }

  /* enable video to create more stress */
  dgEnableVideo(0x100000, 13);

  /* set ebus test mode */
  dgWriteWord(0x04300000, 0x00000400);

  start_address = Register_1_Valid ? Register_1 : DEFAULT_RDRAM_START_ADDRESS;
  end_address = Register_2_Valid ? Register_2 : DEFAULT_RDRAM_END_ADDRESS;

  error_count
    += interleave_test(start_address, end_address, 0x00000000, 0x0000000f, 4);
  error_count
    += interleave_test(start_address, end_address, 0x0000000f, 0x00000000, 4);
  error_count
    += interleave_test(start_address, end_address, 0x00000000, 0x0000000f, 8);
  error_count
    += interleave_test(start_address, end_address, 0x0000000f, 0x00000000, 8);

  return error_count;
}


int
test_random_memory(void) {
  unsigned int start_address;
  unsigned int end_address;
  int repeat;
  int error_count = 0;

  /* enable video to create more stress */
  dgEnableVideo(0x100000, 13);

  start_address = Register_1_Valid ? Register_1 : DEFAULT_RDRAM_START_ADDRESS;
  end_address = Register_2_Valid ? Register_2 : DEFAULT_RDRAM_END_ADDRESS;

  repeat = Register_3_Valid ? Register_3 : 1;
  while (repeat--) {
    error_count += random_test(start_address, end_address, 0xffffffff);
  }
  return error_count;
}


int
test_random_extend(void) {
  unsigned int start_address;
  unsigned int end_address;
  int repeat;
  int error_count = 0;

  if (commtype == DG_TINYMON_RDRAM) {
     return 0;
     }

  /* enable video to create more stress */
  dgEnableVideo(0x100000, 13);

  start_address = Register_1_Valid ? Register_1 : DEFAULT_RDRAM_START_ADDRESS;
  end_address = Register_2_Valid ? Register_2 : DEFAULT_RDRAM_END_ADDRESS;

  repeat = Register_3_Valid ? Register_3 : 1;
  while (repeat--) {
    random_test(start_address, end_address, 0x0000000f);
  }
  return error_count;
}


int
test_random_burst(void)
{
  unsigned int address[RANDOM_BURST_SIZE];
  unsigned int write_data[RANDOM_BURST_SIZE];
  unsigned int read_data;
  unsigned int cycles;
  unsigned int start_address;
  unsigned int end_address;
  int error_count = 0;

  /* enable video to create more stress */
  dgEnableVideo(0x100000, 13);

  start_address = Register_1_Valid ? Register_1 : DEFAULT_RDRAM_START_ADDRESS;
  end_address = Register_2_Valid ? Register_2 : DEFAULT_RDRAM_END_ADDRESS;
  cycles = Register_3_Valid ? Register_3 : DEFAULT_RANDOM_CYCLES;

  srandom(1);
  for ( ; cycles > 0; cycles--) {
    int i, count;
    unsigned int next_address;
    unsigned int found;

    count = random() % RANDOM_BURST_SIZE;

    for (i = 0; i < count; i++) {
      /* create an found aligned address    */
      /* x: start_address <= x < end_address */
      do {
	int j;
	next_address = 0xfffffffc &
	  ((random() % (end_address - start_address)) + start_address);
	for (found = 0, j = 0; !found && (j < i); j++) {
	  found = next_address == address[j];
	}
      } while (found);

      address[i] = next_address;
      write_data[i] = random();

      dgWriteWord(address[i], write_data[i]);

      errlog(DEBUG, "writing - ad = %08x, wr = %08x",
	     address[i], write_data[i]);
    }

    for (i = 0; i < count; i++) {
      dgReadWord(address[i], &read_data);

      errlog(DEBUG, "reading - ad = %08x, rd = %08x",
	     address[i], read_data);

      if (write_data[i] != read_data) {
	errlog(ERR_SEVERE,
	       "data miscompare - ad = %08x, wr = %08x, rd = %08x",
	       address[i], write_data[i], read_data);
	error_count++;
      }
    }
  }
  return error_count;
}


int
bit_test(unsigned int start_address,
	 unsigned int end_address,
	 unsigned int write_data) {

  int i;
  unsigned int read_data;
  int error_count = 0;

  errlog(DEBUG, "Fill RDRAM from %08x to %08x with %08x",
	 start_address, end_address, write_data);
  for (i = start_address; i < end_address; i += 4) {
    dgWriteWord(i, write_data);
  }

  errlog(DEBUG, "Test RDRAM from %08x to %08x for %08x",
	 start_address, end_address, write_data);
  for (i = start_address; i < end_address; i += 4) {
    dgReadWord(i, &read_data);
    if (write_data != read_data) {
      errlog(ERR_SEVERE,
	     "data miscompare - ad = %08x, wr = %08x, rd = %08x",
	     i, write_data, read_data);
      error_count++;
    }
  }
  return error_count;
}


int
interleave_test(unsigned int start_address,
		unsigned int end_address,
		unsigned int pattern_0,
		unsigned int pattern_1,
		unsigned int block_size) {

  int i;
  unsigned int read_data;
  unsigned int write_data;
  int error_count = 0;

  errlog(DEBUG, "Fill %d byte blocks from %08x to %08x with alternating %08x and %08x",
	 block_size, start_address, end_address, pattern_0, pattern_1);

  for (i = start_address; i < end_address; i += 4) {
    write_data = ((i % (block_size*2)) < block_size) ? pattern_0 : pattern_1;
    dgWriteWord(i, write_data);
  }

  errlog(DEBUG, "Test %d byte blocks from %08x to %08x for alternating %08x and %08x",
	 block_size, start_address, end_address, pattern_0, pattern_1);

  for (i = start_address; i < end_address; i += 4) {
    write_data = ((i % (block_size*2)) < block_size) ? pattern_0 : pattern_1;
    dgReadWord(i, &read_data);
    if ((write_data) != (read_data)) {
      errlog(ERR_SEVERE,
	     "data miscompare - ad = %08x, wr = %08x, rd = %08x",
	     i, write_data, read_data);
      error_count++;
    }
  }
  return error_count;
}


int
random_test(unsigned int start_address,
	    unsigned int end_address,
	    unsigned int mask) {

  int i;
  unsigned int read_data;
  unsigned int write_data;
  int error_count = 0;

  errlog(DEBUG, "Fill RDRAM from %08x to %08x with random data",
	 start_address, end_address);

  srandom(1);
  for (i = start_address; i < end_address; i += 4) {
    write_data = random() & mask;
    dgWriteWord(i, write_data);
  }

  errlog(DEBUG, "Test RDRAM from %08x to %08x for random data",
	 start_address, end_address, write_data);

  srandom(1);
  for (i = start_address; i < end_address; i += 4) {
    write_data = random() & mask;
    dgReadWord(i, &read_data);
    read_data &= mask;
    if (write_data != read_data) {
      errlog(ERR_SEVERE,
	     "data miscompare - ad = %08x, wr = %08x, rd = %08x",
	     i, write_data, read_data);
      error_count++;
    }
  }
  return error_count;
}