ndev.config
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/*
* Regman definition for the Nintendo game development card
* (a giobus device accessible via mmap on the host Indy).
*/
define hardware ndev_gio =
{
version = "1.0";
define mmap gioTwoMeg =
{
/*
* Actually, only dram has 16/32 addressing, but regman should always
* fetch 32 bit registers with long word accesses.
*/
addressable_unit_increment = 4;
base = 0xbf400000;
mmap_device_name = "/dev/mmem";
/*
* The third mouse button allows you to bring up a bus browser tool,
* which we will limit to the range of dram memory. A total of 16
* locations will be visible on screen at any time.
*/
dump size = 16;
dump range_max = 0xbf600000;
dump range_min = 0xbf500000;
/*
* Register declarations
*/
define register reg000_productID =
{
address=0:0;
size = 0:8;
read_only = true;
};
/*
* bit <2> at address (base + 0x400) = NMI (to the r4300)
*/
define register reg400_generateNMI =
{
address=0x400:2;
size = 0:1;
write_only = true;
};
/*
* bit <1> at address (base + 0x400) = master reset for
* R4300 & RCP & PIF & friends
*/
define register reg400_generateReset =
{
address=0x400:1;
size = 0:1;
write_only = true;
};
/*
* Cartridge interrupt register. When written to, 6 bits of data
* are available to the R4300 at address 0x18000800 in the R4300's
* address space.
*/
define register reg800_cartInt =
{
address=0x800:0;
size = 0:6;
};
/*
* The 16MB of dram which is mapped to the R4300's rom space is
* accessed 1MB at a time from the GIO bus via the 4 bit select
* value in this register.
*/
define register regA00_dramPageControl =
{
address=0xa00:20;
size = 0:4;
};
/*
* GIO interrupt register. When written to by the R4300 (at address
* 0x18000000 in the R4300's address space), a GIO bus interrupt will
* be generated, and 6 bits of data will be available in this register.
*/
define register regC00_gioInt =
{
address=0xc00:0;
size = 0:6;
read_only = true;
};
/*
* GIO sync register. When written to by the R4300 (at address
* 0x18000400 in the R4300's address space), NO GIO bus interrupt will
* be generated, and 6 bits of data will be available in this register.
*
* It is anticipated that this register will be used in place of the
* gioInterrupt register to implement polling routines in the absence
* of a device driver for the ndev card.
*
*/
define register regE00_gioSync =
{
address=0xe00:0;
size = 0:6;
read_only = true;
};
/*
* Top of DRAM. Provide register definitions for the top & bottom of
* dram so that regman will map the 1 meg of dram space. We'll be able
* to browse dram with the bus browsing tool (which you bring up with
* the third mouse button).
*/
define register gioDramTop =
{
address=0x00100000:0;
size = 0:32;
};
define register gioDramBottom =
{
address=0x001ffffc:0;
size = 0:32;
};
};
};