Makefile 1.6 KB
#!smake -J 5

PRDEPTH = ../../../../..
include $(PRDEPTH)/PRdefs

LVCSOPTS = -y .                                                 \
           -y $(PRDEPTH)/$(HW)/chip/rcp/tc/src                     \
           -y $(PRDEPTH)/$(HW)/chip/rcp/tm/src                     \
           -y $(PRDEPTH)/$(HW)/chip/rcp/ram_bist/src                     \
           -y $(PRDEPTH)/$(HW)/chip/rcp/rdp/src                    \
           -y $(PRDEPTH)/$(HW)/chip/lib/verilog/stdcell                 \
           -y $(PRDEPTH)/$(HW)/chip/lib/verilog/ram                \
           -v $(PRDEPTH)/$(HW)/chip/lib/verilog/udp/compass_udps.v \
            +libext+.v+.vzd                                     \
            +incdir+$(PRDEPTH)/$(HW)/chip/rcp/inc

LDIRT = driver*.v *.mem *.out vcs.log *.dump simv*

TESTS = bist000 
FAST  = fast000 

ERROR = \
	@if grep "ERROR IN SIMULATION" FILE ;		\
	then						\
		echo "";				\
	else						\
		echo "NO ERRORS IN SIMULATION";		\
	fi

default: $(TESTS)

include $(PRDEPTH)/PRrules

.mem.out:

$(TESTS): simv000 

driver000.v: bist000.tab $(TAB2VMEM)
	$(TAB2VMEM) -o /dev/null -s 100 bist000.tab > driver000.v

simv000: top_level.v driver000.v bist000.mem $(_FORCE)
	$(VCS) $(VCSOPTS) -o simv000 -Mdir="bist000" top_level.v driver000.v 
	@ if [ "$(DUMP)" ]; \
	then (echo "simv000 +mem=bist000.mem > simv000.out"; simv000 -vcd verilog000.dump +mem=bist000.mem > simv000.out;) \
	else \
	(echo "simv000 +mem=bist000.mem > simv000.out"; simv000 +mem=bist000.mem +vcs+dumpvarsoff > simv000.out;) \
	fi 
	$(ERROR:FILE=simv000.out)
	$(LOG_ERROR)

fast: $(FAST)	

fast000: bist000.mem
	simv000 +mem=$? | tee $*.out