Makefile
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#!smake
PRDEPTH = ..
include $(PRDEPTH)/PRdefs
#
# Verilog compiler options
#
LVCSOPTS = +incdir+$(PRDEPTH)/hw2/chip/rcp/inc -q
RTLOPTS = -y $(PRDEPTH)/hw2/chip/rcp/ri/src \
-y $(PRDEPTH)/hw2/chip/lib/verilog/rac/behavioral \
-y $(PRDEPTH)/hw2/chip/lib/verilog/rdram/behavioral \
-y $(PRDEPTH)/hw2/chip/lib/verilog/user \
-y $(PRDEPTH)/hw2/chip/lib/verilog/stdcell \
+libext+.v+.vzd \
-Mdir=rtlcsrc
SYNOPTS = -y /hosts/rayden/a/Reality2/mdev2root/PR/hw2/chip/rcp/vsyn \
-y $(PRDEPTH)/hw2/chip/lib/verilog/rac/behavioral \
-y $(PRDEPTH)/hw2/chip/lib/verilog/rdram/behavioral \
-y $(PRDEPTH)/hw2/chip/lib/verilog/user \
-y $(PRDEPTH)/hw2/chip/lib/verilog/stdcell \
+libext+.v+.vsyn \
-Mdir=syncsrc
LDIRT = rsimv rsimv.daidir csrc verilog.dump test???.out
RTESTS = rtest000 rtest001 rtest002 rtest003 rtest004 rtest005 rtest006 \
rtest007 rtest008 rtest009 rtest010 rtest011 rtest012 rtest013 \
rtest014 rtest015
STESTS = stest000 stest001 stest002 stest003 stest004 stest005 stest006 \
stest007 stest008 stest009 stest010 stest011 stest012 stest013 \
stest014 stest015
#DUMP = +dump
default rtests: $(RTESTS)
stests: $(STESTS)
rsimv: top_level.v ri_test.v driver.v driver_tasks.v $(_FORCE)
$(VCS) $(VCSOPTS) $(RTLOPTS) -o $@ top_level.v ri_test.v driver.v
ssimv: top_level.v ri_test.v driver.v driver_tasks.v $(_FORCE)
$(VCS) $(VCSOPTS) $(SYNOPTS) -o $@ top_level.v ri_test.v driver.v
#
# SGI/Project Reality Common Rules
#
include $(PRDEPTH)/PRrules
rtest000: rsimv
rsimv +test000 $(DUMP) > $*.out
$(LOG_RESULT)
rtest001: rsimv
rsimv +test001 $(DUMP) > $*.out
$(LOG_RESULT)
rtest002: rsimv
rsimv +test002 $(DUMP) > $*.out
$(LOG_RESULT)
rtest003: rsimv
rsimv +test003 $(DUMP) > $*.out
$(LOG_RESULT)
rtest004: rsimv
rsimv +test004 $(DUMP) > $*.out
$(LOG_RESULT)
rtest005: rsimv
rsimv +test005 $(DUMP) > $*.out
$(LOG_RESULT)
rtest006: rsimv
rsimv +test006 $(DUMP) > $*.out
$(LOG_RESULT)
rtest007: rsimv
rsimv +test007 $(DUMP) > $*.out
$(LOG_RESULT)
rtest008: rsimv
rsimv +test008 $(DUMP) > $*.out
$(LOG_RESULT)
rtest009: rsimv
rsimv +test009 $(DUMP) > $*.out
$(LOG_RESULT)
rtest010: rsimv
rsimv +test010 $(DUMP) > $*.out
$(LOG_RESULT)
rtest011: rsimv
rsimv +test011 $(DUMP) > $*.out
$(LOG_RESULT)
rtest012: rsimv
rsimv +test012 $(DUMP) > $*.out
$(LOG_RESULT)
rtest013: rsimv
rsimv +test013 $(DUMP) > $*.out
$(LOG_RESULT)
rtest014: rsimv
rsimv +test014 $(DUMP) > $*.out
$(LOG_RESULT)
rtest015: rsimv
rsimv +test015 $(DUMP) > $*.out
$(LOG_RESULT)
stest000: ssimv
ssimv +test000 $(DUMP) > $*.out
$(LOG_RESULT)
stest001: ssimv
ssimv +test001 $(DUMP) > $*.out
$(LOG_RESULT)
stest002: ssimv
ssimv +test002 $(DUMP) > $*.out
$(LOG_RESULT)
stest003: ssimv
ssimv +test003 $(DUMP) > $*.out
$(LOG_RESULT)
stest004: ssimv
ssimv +test004 $(DUMP) > $*.out
$(LOG_RESULT)
stest005: ssimv
ssimv +test005 $(DUMP) > $*.out
$(LOG_RESULT)
stest006: ssimv
ssimv +test006 $(DUMP) > $*.out
$(LOG_RESULT)
stest007: ssimv
ssimv +test007 $(DUMP) > $*.out
$(LOG_RESULT)
stest008: ssimv
ssimv +test008 $(DUMP) > $*.out
$(LOG_RESULT)
stest009: ssimv
ssimv +test009 $(DUMP) > $*.out
$(LOG_RESULT)
stest010: ssimv
ssimv +test010 $(DUMP) > $*.out
$(LOG_RESULT)
stest011: ssimv
ssimv +test011 $(DUMP) > $*.out
$(LOG_RESULT)
stest012: ssimv
ssimv +test012 $(DUMP) > $*.out
$(LOG_RESULT)
stest013: ssimv
ssimv +test013 $(DUMP) > $*.out
$(LOG_RESULT)
stest014: ssimv
ssimv +test014 $(DUMP) > $*.out
$(LOG_RESULT)
stest015: ssimv
ssimv +test015 $(DUMP) > $*.out
$(LOG_RESULT)