/************************************************************************
  WHAT:	RSP REGRESSION TEST GENERATOR - DEFINITIONS
  SCCS: @(#)digen.h	1.2 21 Sep 1994
  PTLS: $Id: digen.h,v 1.1.1.1 2002/05/02 03:29:13 blythe Exp $
  ENGR:	Project Reality - Evan Y. Wang
   (C):	1994 Silicon Graphics, Inc.
 ************************************************************************/
#ifndef _digen_h_
#define _digen_h_

/************************************************************************
  REGISTER (SU and VU) MNEMONICS
 ************************************************************************/
#define Rg		g
#define Rh		h
#define Ri		i
#define Rj		j
#define Rk		k
#define Rm		m

#define R0		0		/* reserved - always zero	*/
#define R1		1		/* if (0x5A5A) passed; else tno;*/
#define R2		2
#define R3		3
#define R4		4
#define R5		5
#define R6		6
#define R7		7
#define R8		8
#define R9		9
#define R10		10
#define R11		11
#define R12		12
#define R13		13
#define R14		14
#define R15		15
#define R16		16
#define R17		17
#define R18		18
#define R19		19
#define R20		20
#define R21		21
#define R22		22
#define R23		23
#define R24		24
#define R25		25
#define R26		26
#define R27		27
#define R28		28
#define R29		29
#define R30		30
#define R31		31		/* reserved as link register	*/

#define Vg		g
#define Vh		h
#define Vi		i
#define Vj		j
#define Vk		k
#define Vm		m

#define V0		0
#define V1		1
#define V2		2
#define V3		3
#define V4		4
#define V5		5
#define V6		6
#define V7		7
#define V8		8
#define V9		9
#define V10		10
#define V11		11
#define V12		12
#define V13		13
#define V14		14
#define V15		15
#define V16		16
#define V17		17
#define V18		18
#define V19		19
#define V20		20
#define V21		21
#define V22		22
#define V23		23
#define V24		24
#define V25		25
#define V26		26
#define V27		27
#define V28		28
#define V29		29
#define V30		30
#define V31		31

#define VCO		0
#define VCC		1
#define VCE		2

#define E0		0
#define E1		1
#define E2		2
#define E3		3
#define E4		4
#define E5		5
#define E6		6
#define E7		7
#define E8		8
#define E9		9
#define E10		10
#define E11		11
#define E12		12
#define E13		13
#define E14		14
#define E15		15

/************************************************************************
  REGISTER FILE DATA STRUCTURE DEFINITIONS
 ************************************************************************/
typedef union {
    u32	w;		/* word				*/
    struct {		/* union within word		*/
	union {		/* high half-word		*/
	    u16 hw;
	    struct {
		u8 hb;	/* high byte of high half-word	*/
		u8 lb;	/* low	byte of high half-word	*/
	    } u;
	} h;
	union {		/* low half-word		*/
	    u16 hw;
	    struct {
		u8 hb;	/* high byte of low half-word	*/
		u8 lb;	/* low	byte of low half-word	*/
	    } u;
	} l;
    } u;
} DATA;

/************************************************************************
  HARDWARE PARAMETERS
 ************************************************************************/
#define IMEM_BASE	0x04001000
#define DMEM_BASE	0x04000000
#define IMEM_SIZE	0x00001000
#define DMEM_SIZE	0x00001000

/************************************************************************
  GLOBAL VARIABLES
 ************************************************************************/
extern DATA	VReg[32][4];
extern DATA	Reg[];
extern u32	IP, Dadr;
extern u16	VCR[];

/************************************************************************
  GENERAL UTILITIES
 ************************************************************************/
#define fpNEWLINE(of)	fprintf(of,"\n")
#define fpDATASEG(of)	fprintf(of,"\t.data\t0x%8.8lX\n",DMEM_BASE)
#define fpDATA(of,d,a)	fprintf(of,"\t.word\t0x%8.8lX\t\t/* Addr: 0x%8.8lX */\n",d,a)
extern void fpCOMMENT();

/************************************************************************
  CONVENIENT MACROS
 ************************************************************************/
#define fpORI(of,r,d)							\
{									\
    fprintf(of,"\tori\t$%d, $0, 0x%4.4X\n", r, d&0xFFFF);		\
    if (r != 0)	 Reg[r].w = d&0xFFFF;					\
    IP+=1;								\
} /* fpORI */

#define fpLIREG(of,r,d)							\
{									\
    fprintf(of,"\tlui\t$%d, 0x%4.4X\n", r, d>>16);			\
    fprintf(of,"\tori\t$%d, $%d, 0x%4.4X\n", r, r, d&0xFFFF);		\
    if (r != 0)	 Reg[r].w = d;						\
    IP+=2;								\
} /* fpLIREG */

#define fpLDVREG(of,v,o,r,w0,w1,w2,w3)					\
{									\
    fpDATA(of,w0,Reg[r].w+o  ); fpDATA(of,w1,Reg[r].w+o+4);		\
    fpDATA(of,w2,Reg[r].w+o+8); fpDATA(of,w3,Reg[r].w+o+12);		\
    fprintf(outp, "\tlqv\t$v%d, 0x%X($%d)\n",v,o,r);			\
    VReg[v][0].w = w0;	VReg[v][1].w = w1;				\
    VReg[v][2].w = w2;	VReg[v][3].w = w3;				\
    IP++;								\
} /* fpLDVREG */

/************************************************************************
  SCALAR UNIT INSTRUCTIONS
 ************************************************************************/
#define fpNOP(of) { fprintf(of,"\tnop\n"); IP++; }

#define fpADD(of,rd,r1,r2)						\
{									\
    fprintf(of,"\tadd\t$%d, $%d, $%d\n",rd,r1,r2);			\
    if (rd != 0) Reg[rd].w = Reg[r1].w + Reg[r2].w;			\
    IP++;								\
} /* fpADD */

#define fpBNE(of,r1,r2)	{ fprintf(of,"\tbne\t$%d, $%d, Fail\n",r1,r2); IP++; }

#define fpBEQ(of,r1,r2)	{ fprintf(of,"\tbeq\t$%d, $%d, Fail\n",r1,r2); IP++; }

#define fpOR(of,rd,r1,r2)						\
{									\
    fprintf(of,"\tor\t$%d, $%d, $%d\n",rd,r1,r2);			\
    if (rd != 0) Reg[rd].w = Reg[r1].w | Reg[r2].w;			\
    IP++;								\
} /* fpOR */

#define fpSW(of,rt,o,rb)						\
{									\
    fprintf(of,"\tsw\t$%d, 0x%X ($%d)\n",rt,o,rb);			\
    IP++;								\
}

#define fpXOR(of,rd,r1,r2)						\
{									\
    fprintf(of,"\txor\t$%d, $%d, $%d\n",rd,r1,r2);			\
    if (rd != 0) Reg[rd].w = Reg[r1].w ^ Reg[r2].w;			\
    IP++;								\
} /* fpXOR */

#define fpCTC2(of,r,v)							\
{									\
    fprintf(of,"\tctc2\t$%d, $v%d\n",r,v);				\
    VCR[v] = Reg[r].w & 0xFFFF;						\
    IP++;								\
} /* fpCTC2 */

#define fpCFC2(of,r,v)							\
{									\
    fprintf(of,"\tcfc2\t$%d, $v%d\n",r,v);				\
    Reg[r].w = VCR[v];							\
    IP++;								\
} /* fpCFC2 */

/************************************************************************
  VECTOR UNIT INSTRUCTIONS
 ************************************************************************/
#define fpLQV(of,vd,o,r) { fprintf(outp, "\tlqv\t$v%d, 0x%X($%d)\n",vd,o,r); IP++; }
#define fpSQV(of,vd,o,r) { fprintf(outp, "\tsqv\t$v%d, 0x%X($%d)\n",vd,o,r); IP++; }

#define fpVNXOR(of,vd,v1,v2)						\
{									\
    fprintf(of,"\tvnxor\t$v%d, $v%d, $v%d\n",vd,v1,v2);			\
    VReg[vd][0].w = ~(VReg[v1][0].w ^ VReg[v2][0].w);			\
    VReg[vd][1].w = ~(VReg[v1][1].w ^ VReg[v2][1].w);			\
    VReg[vd][2].w = ~(VReg[v1][2].w ^ VReg[v2][2].w);			\
    VReg[vd][3].w = ~(VReg[v1][3].w ^ VReg[v2][3].w);			\
    IP++;								\
} /* fpVNXOR */

extern void fpVADD();

extern void fpVEQ();

#endif /* _digen_h_ */