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/************************************************************************
DMA BLOCK READ TESTS: File #1
************************************************************************/
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/****************************************************************
DMA TEST #1.31
****************************************************************/
ori $1, $0, 0x001F /* R1 = TEST ID */
ori $2, $0, 0x0004 /* R2 = 4 */
ori $9, $0, 0x0001 /* R9 = 1 */
ori $10, $0, 0x0788 /* R10 = DMEM ADDRESS */
lui $11, 0x0000 /* R11 = DRAM ADDRESS */
ori $11, $11, 0x27E8
lui $12, 0x4100 /* R12 = READ DMA LEN */
ori $12, $12, 0x2077
mtc0 $10, $0 /* write into CP0 reg */
mtc0 $11, $1 /* write into CP0 reg */
mtc0 $12, $2 /* write into CP0 reg */
Read31: mfc0 $14, $4 /* read status reg */
andi $15, $14, 0x0004 /* extract busy bit */
bne $15, $0, Read31 /* wait for DMA to end */
or $4, $11, $0 /* Init expected data */
or $6, $10, $0 /* R6 = R10 =DMEM addr */
ori $3, $0, 0x0078 /* len of data (bytes) */
ori $7, $0, 0x0002 /* number of spans */
ori $8, $0, 0x0410 /* number of skips */
Chk31: lw $5, 0x0000 ($6) /* read test data */
bne $5, $4, Fail /* verify data */
sub $3, $3, $2 /* decrement counter */
add $4, $4, $2 /* predict next data */
add $6, $6, $2 /* advance DMEM ptr */
bne $3, $0, Chk31 /* check if done */
nop /* bne delay slot */
beq $7, $0, Done31 /* exit if zero span */
ori $3, $0, 0x0078 /* reload len (bytes) */
add $4, $4, $8 /* adjust predict data */
sub $7, $7, $9 /* decrement span cnt */
j Chk31 /* go loop */
Done31:
/****************************************************************
DMA TEST #1.32
****************************************************************/
ori $1, $0, 0x0020 /* R1 = TEST ID */
ori $2, $0, 0x0004 /* R2 = 4 */
ori $9, $0, 0x0001 /* R9 = 1 */
ori $10, $0, 0x0790 /* R10 = DMEM ADDRESS */
lui $11, 0x0000 /* R11 = DRAM ADDRESS */
ori $11, $11, 0x27F0
lui $12, 0x8100 /* R12 = READ DMA LEN */
ori $12, $12, 0x1077
mtc0 $10, $0 /* write into CP0 reg */
mtc0 $11, $1 /* write into CP0 reg */
mtc0 $12, $2 /* write into CP0 reg */
Read32: mfc0 $14, $4 /* read status reg */
andi $15, $14, 0x0004 /* extract busy bit */
bne $15, $0, Read32 /* wait for DMA to end */
or $4, $11, $0 /* Init expected data */
or $6, $10, $0 /* R6 = R10 =DMEM addr */
ori $3, $0, 0x0078 /* len of data (bytes) */
ori $7, $0, 0x0001 /* number of spans */
ori $8, $0, 0x0810 /* number of skips */
Chk32: lw $5, 0x0000 ($6) /* read test data */
bne $5, $4, Fail /* verify data */
sub $3, $3, $2 /* decrement counter */
add $4, $4, $2 /* predict next data */
add $6, $6, $2 /* advance DMEM ptr */
bne $3, $0, Chk32 /* check if done */
nop /* bne delay slot */
beq $7, $0, Done32 /* exit if zero span */
ori $3, $0, 0x0078 /* reload len (bytes) */
add $4, $4, $8 /* adjust predict data */
sub $7, $7, $9 /* decrement span cnt */
j Chk32 /* go loop */
Done32:
/****************************************************************
DMA TEST #1.33
****************************************************************/
ori $1, $0, 0x0021 /* R1 = TEST ID */
ori $2, $0, 0x0004 /* R2 = 4 */
ori $9, $0, 0x0001 /* R9 = 1 */
ori $10, $0, 0x07E8 /* R10 = DMEM ADDRESS */
lui $11, 0x0000 /* R11 = DRAM ADDRESS */
ori $11, $11, 0x27F8
lui $12, 0x0600 /* R12 = READ DMA LEN */
ori $12, $12, 0x2077
mtc0 $10, $0 /* write into CP0 reg */
mtc0 $11, $1 /* write into CP0 reg */
mtc0 $12, $2 /* write into CP0 reg */
Read33: mfc0 $14, $4 /* read status reg */
andi $15, $14, 0x0004 /* extract busy bit */
bne $15, $0, Read33 /* wait for DMA to end */
or $4, $11, $0 /* Init expected data */
or $6, $10, $0 /* R6 = R10 =DMEM addr */
ori $3, $0, 0x0078 /* len of data (bytes) */
ori $7, $0, 0x0002 /* number of spans */
ori $8, $0, 0x0060 /* number of skips */
Chk33: lw $5, 0x0000 ($6) /* read test data */
bne $5, $4, Fail /* verify data */
sub $3, $3, $2 /* decrement counter */
add $4, $4, $2 /* predict next data */
add $6, $6, $2 /* advance DMEM ptr */
bne $3, $0, Chk33 /* check if done */
nop /* bne delay slot */
beq $7, $0, Done33 /* exit if zero span */
ori $3, $0, 0x0078 /* reload len (bytes) */
add $4, $4, $8 /* adjust predict data */
sub $7, $7, $9 /* decrement span cnt */
j Chk33 /* go loop */
Done33:
/****************************************************************
DMA TEST #1.34
****************************************************************/
ori $1, $0, 0x0022 /* R1 = TEST ID */
ori $2, $0, 0x0004 /* R2 = 4 */
ori $9, $0, 0x0001 /* R9 = 1 */
ori $10, $0, 0x07F0 /* R10 = DMEM ADDRESS */
lui $11, 0x0000 /* R11 = DRAM ADDRESS */
ori $11, $11, 0x2800
lui $12, 0x0A00 /* R12 = READ DMA LEN */
ori $12, $12, 0x1077
mtc0 $10, $0 /* write into CP0 reg */
mtc0 $11, $1 /* write into CP0 reg */
mtc0 $12, $2 /* write into CP0 reg */
Read34: mfc0 $14, $4 /* read status reg */
andi $15, $14, 0x0004 /* extract busy bit */
bne $15, $0, Read34 /* wait for DMA to end */
or $4, $11, $0 /* Init expected data */
or $6, $10, $0 /* R6 = R10 =DMEM addr */
ori $3, $0, 0x0078 /* len of data (bytes) */
ori $7, $0, 0x0001 /* number of spans */
ori $8, $0, 0x00A0 /* number of skips */
Chk34: lw $5, 0x0000 ($6) /* read test data */
bne $5, $4, Fail /* verify data */
sub $3, $3, $2 /* decrement counter */
add $4, $4, $2 /* predict next data */
add $6, $6, $2 /* advance DMEM ptr */
bne $3, $0, Chk34 /* check if done */
nop /* bne delay slot */
beq $7, $0, Done34 /* exit if zero span */
ori $3, $0, 0x0078 /* reload len (bytes) */
add $4, $4, $8 /* adjust predict data */
sub $7, $7, $9 /* decrement span cnt */
j Chk34 /* go loop */
Done34:
/****************************************************************
DMA TEST #1.35
****************************************************************/
ori $1, $0, 0x0023 /* R1 = TEST ID */
ori $2, $0, 0x0004 /* R2 = 4 */
ori $9, $0, 0x0001 /* R9 = 1 */
ori $10, $0, 0x07F8 /* R10 = DMEM ADDRESS */
lui $11, 0x0000 /* R11 = DRAM ADDRESS */
ori $11, $11, 0x2808
lui $12, 0x1200 /* R12 = READ DMA LEN */
ori $12, $12, 0x2077
mtc0 $10, $0 /* write into CP0 reg */
mtc0 $11, $1 /* write into CP0 reg */
mtc0 $12, $2 /* write into CP0 reg */
Read35: mfc0 $14, $4 /* read status reg */
andi $15, $14, 0x0004 /* extract busy bit */
bne $15, $0, Read35 /* wait for DMA to end */
or $4, $11, $0 /* Init expected data */
or $6, $10, $0 /* R6 = R10 =DMEM addr */
ori $3, $0, 0x0078 /* len of data (bytes) */
ori $7, $0, 0x0002 /* number of spans */
ori $8, $0, 0x0120 /* number of skips */
Chk35: lw $5, 0x0000 ($6) /* read test data */
bne $5, $4, Fail /* verify data */
sub $3, $3, $2 /* decrement counter */
add $4, $4, $2 /* predict next data */
add $6, $6, $2 /* advance DMEM ptr */
bne $3, $0, Chk35 /* check if done */
nop /* bne delay slot */
beq $7, $0, Done35 /* exit if zero span */
ori $3, $0, 0x0078 /* reload len (bytes) */
add $4, $4, $8 /* adjust predict data */
sub $7, $7, $9 /* decrement span cnt */
j Chk35 /* go loop */
Done35:
/****************************************************************
DMA TEST #1.36
****************************************************************/
ori $1, $0, 0x0024 /* R1 = TEST ID */
ori $2, $0, 0x0004 /* R2 = 4 */
ori $9, $0, 0x0001 /* R9 = 1 */
ori $10, $0, 0x0800 /* R10 = DMEM ADDRESS */
lui $11, 0x0000 /* R11 = DRAM ADDRESS */
ori $11, $11, 0x2F80
lui $12, 0x2200 /* R12 = READ DMA LEN */
ori $12, $12, 0x1077
mtc0 $10, $0 /* write into CP0 reg */
mtc0 $11, $1 /* write into CP0 reg */
mtc0 $12, $2 /* write into CP0 reg */
Read36: mfc0 $14, $4 /* read status reg */
andi $15, $14, 0x0004 /* extract busy bit */
bne $15, $0, Read36 /* wait for DMA to end */
or $4, $11, $0 /* Init expected data */
or $6, $10, $0 /* R6 = R10 =DMEM addr */
ori $3, $0, 0x0078 /* len of data (bytes) */
ori $7, $0, 0x0001 /* number of spans */
ori $8, $0, 0x0220 /* number of skips */
Chk36: lw $5, 0x0000 ($6) /* read test data */
bne $5, $4, Fail /* verify data */
sub $3, $3, $2 /* decrement counter */
add $4, $4, $2 /* predict next data */
add $6, $6, $2 /* advance DMEM ptr */
bne $3, $0, Chk36 /* check if done */
nop /* bne delay slot */
beq $7, $0, Done36 /* exit if zero span */
ori $3, $0, 0x0078 /* reload len (bytes) */
add $4, $4, $8 /* adjust predict data */
sub $7, $7, $9 /* decrement span cnt */
j Chk36 /* go loop */
Done36:
/****************************************************************
DMA TEST #1.37
****************************************************************/
ori $1, $0, 0x0025 /* R1 = TEST ID */
ori $2, $0, 0x0004 /* R2 = 4 */
ori $9, $0, 0x0001 /* R9 = 1 */
ori $10, $0, 0x0808 /* R10 = DMEM ADDRESS */
lui $11, 0x0000 /* R11 = DRAM ADDRESS */
ori $11, $11, 0x2F88
lui $12, 0x4200 /* R12 = READ DMA LEN */
ori $12, $12, 0x2077
mtc0 $10, $0 /* write into CP0 reg */
mtc0 $11, $1 /* write into CP0 reg */
mtc0 $12, $2 /* write into CP0 reg */
Read37: mfc0 $14, $4 /* read status reg */
andi $15, $14, 0x0004 /* extract busy bit */
bne $15, $0, Read37 /* wait for DMA to end */
or $4, $11, $0 /* Init expected data */
or $6, $10, $0 /* R6 = R10 =DMEM addr */
ori $3, $0, 0x0078 /* len of data (bytes) */
ori $7, $0, 0x0002 /* number of spans */
ori $8, $0, 0x0420 /* number of skips */
Chk37: lw $5, 0x0000 ($6) /* read test data */
bne $5, $4, Fail /* verify data */
sub $3, $3, $2 /* decrement counter */
add $4, $4, $2 /* predict next data */
add $6, $6, $2 /* advance DMEM ptr */
bne $3, $0, Chk37 /* check if done */
nop /* bne delay slot */
beq $7, $0, Done37 /* exit if zero span */
ori $3, $0, 0x0078 /* reload len (bytes) */
add $4, $4, $8 /* adjust predict data */
sub $7, $7, $9 /* decrement span cnt */
j Chk37 /* go loop */
Done37:
/****************************************************************
DMA TEST #1.38
****************************************************************/
ori $1, $0, 0x0026 /* R1 = TEST ID */
ori $2, $0, 0x0004 /* R2 = 4 */
ori $9, $0, 0x0001 /* R9 = 1 */
ori $10, $0, 0x0F80 /* R10 = DMEM ADDRESS */
lui $11, 0x0000 /* R11 = DRAM ADDRESS */
ori $11, $11, 0x2F90
lui $12, 0xFF80 /* R12 = READ DMA LEN */
ori $12, $12, 0x0077
mtc0 $10, $0 /* write into CP0 reg */
mtc0 $11, $1 /* write into CP0 reg */
mtc0 $12, $2 /* write into CP0 reg */
Read38: mfc0 $14, $4 /* read status reg */
andi $15, $14, 0x0004 /* extract busy bit */
bne $15, $0, Read38 /* wait for DMA to end */
or $4, $11, $0 /* Init expected data */
or $6, $10, $0 /* R6 = R10 =DMEM addr */
ori $3, $0, 0x0078 /* len of data (bytes) */
ori $7, $0, 0x0000 /* number of spans */
ori $8, $0, 0x0FF8 /* number of skips */
Chk38: lw $5, 0x0000 ($6) /* read test data */
bne $5, $4, Fail /* verify data */
sub $3, $3, $2 /* decrement counter */
add $4, $4, $2 /* predict next data */
add $6, $6, $2 /* advance DMEM ptr */
bne $3, $0, Chk38 /* check if done */
nop /* bne delay slot */
beq $7, $0, Done38 /* exit if zero span */
ori $3, $0, 0x0078 /* reload len (bytes) */
add $4, $4, $8 /* adjust predict data */
sub $7, $7, $9 /* decrement span cnt */
j Chk38 /* go loop */
Done38:
/****************************************************************
DMA TEST #1.39
****************************************************************/
ori $1, $0, 0x0027 /* R1 = TEST ID */
ori $2, $0, 0x0004 /* R2 = 4 */
ori $9, $0, 0x0001 /* R9 = 1 */
ori $10, $0, 0x0F88 /* R10 = DMEM ADDRESS */
lui $11, 0x0000 /* R11 = DRAM ADDRESS */
ori $11, $11, 0x2FF8
lui $12, 0xFF80 /* R12 = READ DMA LEN */
ori $12, $12, 0x0077
mtc0 $10, $0 /* write into CP0 reg */
mtc0 $11, $1 /* write into CP0 reg */
mtc0 $12, $2 /* write into CP0 reg */
Read39: mfc0 $14, $4 /* read status reg */
andi $15, $14, 0x0004 /* extract busy bit */
bne $15, $0, Read39 /* wait for DMA to end */
or $4, $11, $0 /* Init expected data */
or $6, $10, $0 /* R6 = R10 =DMEM addr */
ori $3, $0, 0x0078 /* len of data (bytes) */
ori $7, $0, 0x0000 /* number of spans */
ori $8, $0, 0x0FF8 /* number of skips */
Chk39: lw $5, 0x0000 ($6) /* read test data */
bne $5, $4, Fail /* verify data */
sub $3, $3, $2 /* decrement counter */
add $4, $4, $2 /* predict next data */
add $6, $6, $2 /* advance DMEM ptr */
bne $3, $0, Chk39 /* check if done */
nop /* bne delay slot */
beq $7, $0, Done39 /* exit if zero span */
ori $3, $0, 0x0078 /* reload len (bytes) */
add $4, $4, $8 /* adjust predict data */
sub $7, $7, $9 /* decrement span cnt */
j Chk39 /* go loop */
Done39:
/****************************************************************
DMA TEST #1.40
****************************************************************/
ori $1, $0, 0x0028 /* R1 = TEST ID */
ori $2, $0, 0x0004 /* R2 = 4 */
ori $9, $0, 0x0001 /* R9 = 1 */
ori $10, $0, 0x0000 /* R10 = DMEM ADDRESS */
lui $11, 0x0000 /* R11 = DRAM ADDRESS */
ori $11, $11, 0x2778
lui $12, 0x0080 /* R12 = READ DMA LEN */
ori $12, $12, 0x107F
mtc0 $10, $0 /* write into CP0 reg */
mtc0 $11, $1 /* write into CP0 reg */
mtc0 $12, $2 /* write into CP0 reg */
Read40: mfc0 $14, $4 /* read status reg */
andi $15, $14, 0x0004 /* extract busy bit */
bne $15, $0, Read40 /* wait for DMA to end */
or $4, $11, $0 /* Init expected data */
or $6, $10, $0 /* R6 = R10 =DMEM addr */
ori $3, $0, 0x0080 /* len of data (bytes) */
ori $7, $0, 0x0001 /* number of spans */
ori $8, $0, 0x0008 /* number of skips */
Chk40: lw $5, 0x0000 ($6) /* read test data */
bne $5, $4, Fail /* verify data */
sub $3, $3, $2 /* decrement counter */
add $4, $4, $2 /* predict next data */
add $6, $6, $2 /* advance DMEM ptr */
bne $3, $0, Chk40 /* check if done */
nop /* bne delay slot */
beq $7, $0, Done40 /* exit if zero span */
ori $3, $0, 0x0080 /* reload len (bytes) */
add $4, $4, $8 /* adjust predict data */
sub $7, $7, $9 /* decrement span cnt */
j Chk40 /* go loop */
Done40:
/****************************************************************
DMA TEST #1.41
****************************************************************/
ori $1, $0, 0x0029 /* R1 = TEST ID */
ori $2, $0, 0x0004 /* R2 = 4 */
ori $9, $0, 0x0001 /* R9 = 1 */
ori $10, $0, 0x0008 /* R10 = DMEM ADDRESS */
lui $11, 0x0000 /* R11 = DRAM ADDRESS */
ori $11, $11, 0x2780
lui $12, 0x0100 /* R12 = READ DMA LEN */
ori $12, $12, 0x207F
mtc0 $10, $0 /* write into CP0 reg */
mtc0 $11, $1 /* write into CP0 reg */
mtc0 $12, $2 /* write into CP0 reg */
Read41: mfc0 $14, $4 /* read status reg */
andi $15, $14, 0x0004 /* extract busy bit */
bne $15, $0, Read41 /* wait for DMA to end */
or $4, $11, $0 /* Init expected data */
or $6, $10, $0 /* R6 = R10 =DMEM addr */
ori $3, $0, 0x0080 /* len of data (bytes) */
ori $7, $0, 0x0002 /* number of spans */
ori $8, $0, 0x0010 /* number of skips */
Chk41: lw $5, 0x0000 ($6) /* read test data */
bne $5, $4, Fail /* verify data */
sub $3, $3, $2 /* decrement counter */
add $4, $4, $2 /* predict next data */
add $6, $6, $2 /* advance DMEM ptr */
bne $3, $0, Chk41 /* check if done */
nop /* bne delay slot */
beq $7, $0, Done41 /* exit if zero span */
ori $3, $0, 0x0080 /* reload len (bytes) */
add $4, $4, $8 /* adjust predict data */
sub $7, $7, $9 /* decrement span cnt */
j Chk41 /* go loop */
Done41:
/****************************************************************
DMA TEST #1.42
****************************************************************/
ori $1, $0, 0x002A /* R1 = TEST ID */
ori $2, $0, 0x0004 /* R2 = 4 */
ori $9, $0, 0x0001 /* R9 = 1 */
ori $10, $0, 0x0778 /* R10 = DMEM ADDRESS */
lui $11, 0x0000 /* R11 = DRAM ADDRESS */
ori $11, $11, 0x2788
lui $12, 0x0180 /* R12 = READ DMA LEN */
ori $12, $12, 0x107F
mtc0 $10, $0 /* write into CP0 reg */
mtc0 $11, $1 /* write into CP0 reg */
mtc0 $12, $2 /* write into CP0 reg */
Read42: mfc0 $14, $4 /* read status reg */
andi $15, $14, 0x0004 /* extract busy bit */
bne $15, $0, Read42 /* wait for DMA to end */
or $4, $11, $0 /* Init expected data */
or $6, $10, $0 /* R6 = R10 =DMEM addr */
ori $3, $0, 0x0080 /* len of data (bytes) */
ori $7, $0, 0x0001 /* number of spans */
ori $8, $0, 0x0018 /* number of skips */
Chk42: lw $5, 0x0000 ($6) /* read test data */
bne $5, $4, Fail /* verify data */
sub $3, $3, $2 /* decrement counter */
add $4, $4, $2 /* predict next data */
add $6, $6, $2 /* advance DMEM ptr */
bne $3, $0, Chk42 /* check if done */
nop /* bne delay slot */
beq $7, $0, Done42 /* exit if zero span */
ori $3, $0, 0x0080 /* reload len (bytes) */
add $4, $4, $8 /* adjust predict data */
sub $7, $7, $9 /* decrement span cnt */
j Chk42 /* go loop */
Done42:
/****************************************************************
DMA TEST #1.43
****************************************************************/
ori $1, $0, 0x002B /* R1 = TEST ID */
ori $2, $0, 0x0004 /* R2 = 4 */
ori $9, $0, 0x0001 /* R9 = 1 */
ori $10, $0, 0x0780 /* R10 = DMEM ADDRESS */
lui $11, 0x0000 /* R11 = DRAM ADDRESS */
ori $11, $11, 0x27E8
lui $12, 0x0200 /* R12 = READ DMA LEN */
ori $12, $12, 0x207F
mtc0 $10, $0 /* write into CP0 reg */
mtc0 $11, $1 /* write into CP0 reg */
mtc0 $12, $2 /* write into CP0 reg */
Read43: mfc0 $14, $4 /* read status reg */
andi $15, $14, 0x0004 /* extract busy bit */
bne $15, $0, Read43 /* wait for DMA to end */
or $4, $11, $0 /* Init expected data */
or $6, $10, $0 /* R6 = R10 =DMEM addr */
ori $3, $0, 0x0080 /* len of data (bytes) */
ori $7, $0, 0x0002 /* number of spans */
ori $8, $0, 0x0020 /* number of skips */
Chk43: lw $5, 0x0000 ($6) /* read test data */
bne $5, $4, Fail /* verify data */
sub $3, $3, $2 /* decrement counter */
add $4, $4, $2 /* predict next data */
add $6, $6, $2 /* advance DMEM ptr */
bne $3, $0, Chk43 /* check if done */
nop /* bne delay slot */
beq $7, $0, Done43 /* exit if zero span */
ori $3, $0, 0x0080 /* reload len (bytes) */
add $4, $4, $8 /* adjust predict data */
sub $7, $7, $9 /* decrement span cnt */
j Chk43 /* go loop */
Done43:
/****************************************************************
DMA TEST #1.44
****************************************************************/
ori $1, $0, 0x002C /* R1 = TEST ID */
ori $2, $0, 0x0004 /* R2 = 4 */
ori $9, $0, 0x0001 /* R9 = 1 */
ori $10, $0, 0x0788 /* R10 = DMEM ADDRESS */
lui $11, 0x0000 /* R11 = DRAM ADDRESS */
ori $11, $11, 0x27F0
lui $12, 0x0280 /* R12 = READ DMA LEN */
ori $12, $12, 0x107F
mtc0 $10, $0 /* write into CP0 reg */
mtc0 $11, $1 /* write into CP0 reg */
mtc0 $12, $2 /* write into CP0 reg */
Read44: mfc0 $14, $4 /* read status reg */
andi $15, $14, 0x0004 /* extract busy bit */
bne $15, $0, Read44 /* wait for DMA to end */
or $4, $11, $0 /* Init expected data */
or $6, $10, $0 /* R6 = R10 =DMEM addr */
ori $3, $0, 0x0080 /* len of data (bytes) */
ori $7, $0, 0x0001 /* number of spans */
ori $8, $0, 0x0028 /* number of skips */
Chk44: lw $5, 0x0000 ($6) /* read test data */
bne $5, $4, Fail /* verify data */
sub $3, $3, $2 /* decrement counter */
add $4, $4, $2 /* predict next data */
add $6, $6, $2 /* advance DMEM ptr */
bne $3, $0, Chk44 /* check if done */
nop /* bne delay slot */
beq $7, $0, Done44 /* exit if zero span */
ori $3, $0, 0x0080 /* reload len (bytes) */
add $4, $4, $8 /* adjust predict data */
sub $7, $7, $9 /* decrement span cnt */
j Chk44 /* go loop */
Done44:
/****************************************************************
DMA TEST #1.45
****************************************************************/
ori $1, $0, 0x002D /* R1 = TEST ID */
ori $2, $0, 0x0004 /* R2 = 4 */
ori $9, $0, 0x0001 /* R9 = 1 */
ori $10, $0, 0x07E8 /* R10 = DMEM ADDRESS */
lui $11, 0x0000 /* R11 = DRAM ADDRESS */
ori $11, $11, 0x27F8
lui $12, 0x0300 /* R12 = READ DMA LEN */
ori $12, $12, 0x207F
mtc0 $10, $0 /* write into CP0 reg */
mtc0 $11, $1 /* write into CP0 reg */
mtc0 $12, $2 /* write into CP0 reg */
Read45: mfc0 $14, $4 /* read status reg */
andi $15, $14, 0x0004 /* extract busy bit */
bne $15, $0, Read45 /* wait for DMA to end */
or $4, $11, $0 /* Init expected data */
or $6, $10, $0 /* R6 = R10 =DMEM addr */
ori $3, $0, 0x0080 /* len of data (bytes) */
ori $7, $0, 0x0002 /* number of spans */
ori $8, $0, 0x0030 /* number of skips */
Chk45: lw $5, 0x0000 ($6) /* read test data */
bne $5, $4, Fail /* verify data */
sub $3, $3, $2 /* decrement counter */
add $4, $4, $2 /* predict next data */
add $6, $6, $2 /* advance DMEM ptr */
bne $3, $0, Chk45 /* check if done */
nop /* bne delay slot */
beq $7, $0, Done45 /* exit if zero span */
ori $3, $0, 0x0080 /* reload len (bytes) */
add $4, $4, $8 /* adjust predict data */
sub $7, $7, $9 /* decrement span cnt */
j Chk45 /* go loop */
Done45:
/****************************************************************
DMA TEST #1.46
****************************************************************/
ori $1, $0, 0x002E /* R1 = TEST ID */
ori $2, $0, 0x0004 /* R2 = 4 */
ori $9, $0, 0x0001 /* R9 = 1 */
ori $10, $0, 0x07F0 /* R10 = DMEM ADDRESS */
lui $11, 0x0000 /* R11 = DRAM ADDRESS */
ori $11, $11, 0x2800
lui $12, 0x0380 /* R12 = READ DMA LEN */
ori $12, $12, 0x107F
mtc0 $10, $0 /* write into CP0 reg */
mtc0 $11, $1 /* write into CP0 reg */
mtc0 $12, $2 /* write into CP0 reg */
Read46: mfc0 $14, $4 /* read status reg */
andi $15, $14, 0x0004 /* extract busy bit */
bne $15, $0, Read46 /* wait for DMA to end */
or $4, $11, $0 /* Init expected data */
or $6, $10, $0 /* R6 = R10 =DMEM addr */
ori $3, $0, 0x0080 /* len of data (bytes) */
ori $7, $0, 0x0001 /* number of spans */
ori $8, $0, 0x0038 /* number of skips */
Chk46: lw $5, 0x0000 ($6) /* read test data */
bne $5, $4, Fail /* verify data */
sub $3, $3, $2 /* decrement counter */
add $4, $4, $2 /* predict next data */
add $6, $6, $2 /* advance DMEM ptr */
bne $3, $0, Chk46 /* check if done */
nop /* bne delay slot */
beq $7, $0, Done46 /* exit if zero span */
ori $3, $0, 0x0080 /* reload len (bytes) */
add $4, $4, $8 /* adjust predict data */
sub $7, $7, $9 /* decrement span cnt */
j Chk46 /* go loop */
Done46:
/****************************************************************
DMA TEST #1.47
****************************************************************/
ori $1, $0, 0x002F /* R1 = TEST ID */
ori $2, $0, 0x0004 /* R2 = 4 */
ori $9, $0, 0x0001 /* R9 = 1 */
ori $10, $0, 0x07F8 /* R10 = DMEM ADDRESS */
lui $11, 0x0000 /* R11 = DRAM ADDRESS */
ori $11, $11, 0x2808
lui $12, 0x0400 /* R12 = READ DMA LEN */
ori $12, $12, 0x207F
mtc0 $10, $0 /* write into CP0 reg */
mtc0 $11, $1 /* write into CP0 reg */
mtc0 $12, $2 /* write into CP0 reg */
Read47: mfc0 $14, $4 /* read status reg */
andi $15, $14, 0x0004 /* extract busy bit */
bne $15, $0, Read47 /* wait for DMA to end */
or $4, $11, $0 /* Init expected data */
or $6, $10, $0 /* R6 = R10 =DMEM addr */
ori $3, $0, 0x0080 /* len of data (bytes) */
ori $7, $0, 0x0002 /* number of spans */
ori $8, $0, 0x0040 /* number of skips */
Chk47: lw $5, 0x0000 ($6) /* read test data */
bne $5, $4, Fail /* verify data */
sub $3, $3, $2 /* decrement counter */
add $4, $4, $2 /* predict next data */
add $6, $6, $2 /* advance DMEM ptr */
bne $3, $0, Chk47 /* check if done */
nop /* bne delay slot */
beq $7, $0, Done47 /* exit if zero span */
ori $3, $0, 0x0080 /* reload len (bytes) */
add $4, $4, $8 /* adjust predict data */
sub $7, $7, $9 /* decrement span cnt */
j Chk47 /* go loop */
Done47:
/****************************************************************
DMA TEST #1.48
****************************************************************/
ori $1, $0, 0x0030 /* R1 = TEST ID */
ori $2, $0, 0x0004 /* R2 = 4 */
ori $9, $0, 0x0001 /* R9 = 1 */
ori $10, $0, 0x0800 /* R10 = DMEM ADDRESS */
lui $11, 0x0000 /* R11 = DRAM ADDRESS */
ori $11, $11, 0x2F78
lui $12, 0x0480 /* R12 = READ DMA LEN */
ori $12, $12, 0x107F
mtc0 $10, $0 /* write into CP0 reg */
mtc0 $11, $1 /* write into CP0 reg */
mtc0 $12, $2 /* write into CP0 reg */
Read48: mfc0 $14, $4 /* read status reg */
andi $15, $14, 0x0004 /* extract busy bit */
bne $15, $0, Read48 /* wait for DMA to end */
or $4, $11, $0 /* Init expected data */
or $6, $10, $0 /* R6 = R10 =DMEM addr */
ori $3, $0, 0x0080 /* len of data (bytes) */
ori $7, $0, 0x0001 /* number of spans */
ori $8, $0, 0x0048 /* number of skips */
Chk48: lw $5, 0x0000 ($6) /* read test data */
bne $5, $4, Fail /* verify data */
sub $3, $3, $2 /* decrement counter */
add $4, $4, $2 /* predict next data */
add $6, $6, $2 /* advance DMEM ptr */
bne $3, $0, Chk48 /* check if done */
nop /* bne delay slot */
beq $7, $0, Done48 /* exit if zero span */
ori $3, $0, 0x0080 /* reload len (bytes) */
add $4, $4, $8 /* adjust predict data */
sub $7, $7, $9 /* decrement span cnt */
j Chk48 /* go loop */
Done48:
/****************************************************************
DMA TEST #1.49
****************************************************************/
ori $1, $0, 0x0031 /* R1 = TEST ID */
ori $2, $0, 0x0004 /* R2 = 4 */
ori $9, $0, 0x0001 /* R9 = 1 */
ori $10, $0, 0x0808 /* R10 = DMEM ADDRESS */
lui $11, 0x0000 /* R11 = DRAM ADDRESS */
ori $11, $11, 0x2F80
lui $12, 0x0500 /* R12 = READ DMA LEN */
ori $12, $12, 0x207F
mtc0 $10, $0 /* write into CP0 reg */
mtc0 $11, $1 /* write into CP0 reg */
mtc0 $12, $2 /* write into CP0 reg */
Read49: mfc0 $14, $4 /* read status reg */
andi $15, $14, 0x0004 /* extract busy bit */
bne $15, $0, Read49 /* wait for DMA to end */
or $4, $11, $0 /* Init expected data */
or $6, $10, $0 /* R6 = R10 =DMEM addr */
ori $3, $0, 0x0080 /* len of data (bytes) */
ori $7, $0, 0x0002 /* number of spans */
ori $8, $0, 0x0050 /* number of skips */
Chk49: lw $5, 0x0000 ($6) /* read test data */
bne $5, $4, Fail /* verify data */
sub $3, $3, $2 /* decrement counter */
add $4, $4, $2 /* predict next data */
add $6, $6, $2 /* advance DMEM ptr */
bne $3, $0, Chk49 /* check if done */
nop /* bne delay slot */
beq $7, $0, Done49 /* exit if zero span */
ori $3, $0, 0x0080 /* reload len (bytes) */
add $4, $4, $8 /* adjust predict data */
sub $7, $7, $9 /* decrement span cnt */
j Chk49 /* go loop */
Done49:
/****************************************************************
DMA TEST #1.50
****************************************************************/
ori $1, $0, 0x0032 /* R1 = TEST ID */
ori $2, $0, 0x0004 /* R2 = 4 */
ori $9, $0, 0x0001 /* R9 = 1 */
ori $10, $0, 0x0F78 /* R10 = DMEM ADDRESS */
lui $11, 0x0000 /* R11 = DRAM ADDRESS */
ori $11, $11, 0x2F88
lui $12, 0xFF80 /* R12 = READ DMA LEN */
ori $12, $12, 0x007F
mtc0 $10, $0 /* write into CP0 reg */
mtc0 $11, $1 /* write into CP0 reg */
mtc0 $12, $2 /* write into CP0 reg */
Read50: mfc0 $14, $4 /* read status reg */
andi $15, $14, 0x0004 /* extract busy bit */
bne $15, $0, Read50 /* wait for DMA to end */
or $4, $11, $0 /* Init expected data */
or $6, $10, $0 /* R6 = R10 =DMEM addr */
ori $3, $0, 0x0080 /* len of data (bytes) */
ori $7, $0, 0x0000 /* number of spans */
ori $8, $0, 0x0FF8 /* number of skips */
Chk50: lw $5, 0x0000 ($6) /* read test data */
bne $5, $4, Fail /* verify data */
sub $3, $3, $2 /* decrement counter */
add $4, $4, $2 /* predict next data */
add $6, $6, $2 /* advance DMEM ptr */
bne $3, $0, Chk50 /* check if done */
nop /* bne delay slot */
beq $7, $0, Done50 /* exit if zero span */
ori $3, $0, 0x0080 /* reload len (bytes) */
add $4, $4, $8 /* adjust predict data */
sub $7, $7, $9 /* decrement span cnt */
j Chk50 /* go loop */
Done50:
/****************************************************************
DMA TEST #1.51
****************************************************************/
ori $1, $0, 0x0033 /* R1 = TEST ID */
ori $2, $0, 0x0004 /* R2 = 4 */
ori $9, $0, 0x0001 /* R9 = 1 */
ori $10, $0, 0x0F80 /* R10 = DMEM ADDRESS */
lui $11, 0x0000 /* R11 = DRAM ADDRESS */
ori $11, $11, 0x2FF8
lui $12, 0xFF80 /* R12 = READ DMA LEN */
ori $12, $12, 0x007F
mtc0 $10, $0 /* write into CP0 reg */
mtc0 $11, $1 /* write into CP0 reg */
mtc0 $12, $2 /* write into CP0 reg */
Read51: mfc0 $14, $4 /* read status reg */
andi $15, $14, 0x0004 /* extract busy bit */
bne $15, $0, Read51 /* wait for DMA to end */
or $4, $11, $0 /* Init expected data */
or $6, $10, $0 /* R6 = R10 =DMEM addr */
ori $3, $0, 0x0080 /* len of data (bytes) */
ori $7, $0, 0x0000 /* number of spans */
ori $8, $0, 0x0FF8 /* number of skips */
Chk51: lw $5, 0x0000 ($6) /* read test data */
bne $5, $4, Fail /* verify data */
sub $3, $3, $2 /* decrement counter */
add $4, $4, $2 /* predict next data */
add $6, $6, $2 /* advance DMEM ptr */
bne $3, $0, Chk51 /* check if done */
nop /* bne delay slot */
beq $7, $0, Done51 /* exit if zero span */
ori $3, $0, 0x0080 /* reload len (bytes) */
add $4, $4, $8 /* adjust predict data */
sub $7, $7, $9 /* decrement span cnt */
j Chk51 /* go loop */
Done51:
/****************************************************************
DMA TEST #1.52
****************************************************************/
ori $1, $0, 0x0034 /* R1 = TEST ID */
ori $2, $0, 0x0004 /* R2 = 4 */
ori $9, $0, 0x0001 /* R9 = 1 */
ori $10, $0, 0x0000 /* R10 = DMEM ADDRESS */
lui $11, 0x0000 /* R11 = DRAM ADDRESS */
ori $11, $11, 0x2770
lui $12, 0x0580 /* R12 = READ DMA LEN */
ori $12, $12, 0x107F
mtc0 $10, $0 /* write into CP0 reg */
mtc0 $11, $1 /* write into CP0 reg */
mtc0 $12, $2 /* write into CP0 reg */
Read52: mfc0 $14, $4 /* read status reg */
andi $15, $14, 0x0004 /* extract busy bit */
bne $15, $0, Read52 /* wait for DMA to end */
or $4, $11, $0 /* Init expected data */
or $6, $10, $0 /* R6 = R10 =DMEM addr */
ori $3, $0, 0x0080 /* len of data (bytes) */
ori $7, $0, 0x0001 /* number of spans */
ori $8, $0, 0x0058 /* number of skips */
Chk52: lw $5, 0x0000 ($6) /* read test data */
bne $5, $4, Fail /* verify data */
sub $3, $3, $2 /* decrement counter */
add $4, $4, $2 /* predict next data */
add $6, $6, $2 /* advance DMEM ptr */
bne $3, $0, Chk52 /* check if done */
nop /* bne delay slot */
beq $7, $0, Done52 /* exit if zero span */
ori $3, $0, 0x0080 /* reload len (bytes) */
add $4, $4, $8 /* adjust predict data */
sub $7, $7, $9 /* decrement span cnt */
j Chk52 /* go loop */
Done52:
/****************************************************************
DMA TEST #1.53
****************************************************************/
ori $1, $0, 0x0035 /* R1 = TEST ID */
ori $2, $0, 0x0004 /* R2 = 4 */
ori $9, $0, 0x0001 /* R9 = 1 */
ori $10, $0, 0x0008 /* R10 = DMEM ADDRESS */
lui $11, 0x0000 /* R11 = DRAM ADDRESS */
ori $11, $11, 0x2778
lui $12, 0x0600 /* R12 = READ DMA LEN */
ori $12, $12, 0x207F
mtc0 $10, $0 /* write into CP0 reg */
mtc0 $11, $1 /* write into CP0 reg */
mtc0 $12, $2 /* write into CP0 reg */
Read53: mfc0 $14, $4 /* read status reg */
andi $15, $14, 0x0004 /* extract busy bit */
bne $15, $0, Read53 /* wait for DMA to end */
or $4, $11, $0 /* Init expected data */
or $6, $10, $0 /* R6 = R10 =DMEM addr */
ori $3, $0, 0x0080 /* len of data (bytes) */
ori $7, $0, 0x0002 /* number of spans */
ori $8, $0, 0x0060 /* number of skips */
Chk53: lw $5, 0x0000 ($6) /* read test data */
bne $5, $4, Fail /* verify data */
sub $3, $3, $2 /* decrement counter */
add $4, $4, $2 /* predict next data */
add $6, $6, $2 /* advance DMEM ptr */
bne $3, $0, Chk53 /* check if done */
nop /* bne delay slot */
beq $7, $0, Done53 /* exit if zero span */
ori $3, $0, 0x0080 /* reload len (bytes) */
add $4, $4, $8 /* adjust predict data */
sub $7, $7, $9 /* decrement span cnt */
j Chk53 /* go loop */
Done53:
/****************************************************************
DMA TEST #1.54
****************************************************************/
ori $1, $0, 0x0036 /* R1 = TEST ID */
ori $2, $0, 0x0004 /* R2 = 4 */
ori $9, $0, 0x0001 /* R9 = 1 */
ori $10, $0, 0x0770 /* R10 = DMEM ADDRESS */
lui $11, 0x0000 /* R11 = DRAM ADDRESS */
ori $11, $11, 0x2780
lui $12, 0x0680 /* R12 = READ DMA LEN */
ori $12, $12, 0x107F
mtc0 $10, $0 /* write into CP0 reg */
mtc0 $11, $1 /* write into CP0 reg */
mtc0 $12, $2 /* write into CP0 reg */
Read54: mfc0 $14, $4 /* read status reg */
andi $15, $14, 0x0004 /* extract busy bit */
bne $15, $0, Read54 /* wait for DMA to end */
or $4, $11, $0 /* Init expected data */
or $6, $10, $0 /* R6 = R10 =DMEM addr */
ori $3, $0, 0x0080 /* len of data (bytes) */
ori $7, $0, 0x0001 /* number of spans */
ori $8, $0, 0x0068 /* number of skips */
Chk54: lw $5, 0x0000 ($6) /* read test data */
bne $5, $4, Fail /* verify data */
sub $3, $3, $2 /* decrement counter */
add $4, $4, $2 /* predict next data */
add $6, $6, $2 /* advance DMEM ptr */
bne $3, $0, Chk54 /* check if done */
nop /* bne delay slot */
beq $7, $0, Done54 /* exit if zero span */
ori $3, $0, 0x0080 /* reload len (bytes) */
add $4, $4, $8 /* adjust predict data */
sub $7, $7, $9 /* decrement span cnt */
j Chk54 /* go loop */
Done54:
/****************************************************************
DMA TEST #1.55
****************************************************************/
ori $1, $0, 0x0037 /* R1 = TEST ID */
ori $2, $0, 0x0004 /* R2 = 4 */
ori $9, $0, 0x0001 /* R9 = 1 */
ori $10, $0, 0x0778 /* R10 = DMEM ADDRESS */
lui $11, 0x0000 /* R11 = DRAM ADDRESS */
ori $11, $11, 0x27E8
lui $12, 0x0700 /* R12 = READ DMA LEN */
ori $12, $12, 0x207F
mtc0 $10, $0 /* write into CP0 reg */
mtc0 $11, $1 /* write into CP0 reg */
mtc0 $12, $2 /* write into CP0 reg */
Read55: mfc0 $14, $4 /* read status reg */
andi $15, $14, 0x0004 /* extract busy bit */
bne $15, $0, Read55 /* wait for DMA to end */
or $4, $11, $0 /* Init expected data */
or $6, $10, $0 /* R6 = R10 =DMEM addr */
ori $3, $0, 0x0080 /* len of data (bytes) */
ori $7, $0, 0x0002 /* number of spans */
ori $8, $0, 0x0070 /* number of skips */
Chk55: lw $5, 0x0000 ($6) /* read test data */
bne $5, $4, Fail /* verify data */
sub $3, $3, $2 /* decrement counter */
add $4, $4, $2 /* predict next data */
add $6, $6, $2 /* advance DMEM ptr */
bne $3, $0, Chk55 /* check if done */
nop /* bne delay slot */
beq $7, $0, Done55 /* exit if zero span */
ori $3, $0, 0x0080 /* reload len (bytes) */
add $4, $4, $8 /* adjust predict data */
sub $7, $7, $9 /* decrement span cnt */
j Chk55 /* go loop */
Done55:
/****************************************************************
DMA TEST #1.56
****************************************************************/
ori $1, $0, 0x0038 /* R1 = TEST ID */
ori $2, $0, 0x0004 /* R2 = 4 */
ori $9, $0, 0x0001 /* R9 = 1 */
ori $10, $0, 0x0780 /* R10 = DMEM ADDRESS */
lui $11, 0x0000 /* R11 = DRAM ADDRESS */
ori $11, $11, 0x27F0
lui $12, 0x0780 /* R12 = READ DMA LEN */
ori $12, $12, 0x107F
mtc0 $10, $0 /* write into CP0 reg */
mtc0 $11, $1 /* write into CP0 reg */
mtc0 $12, $2 /* write into CP0 reg */
Read56: mfc0 $14, $4 /* read status reg */
andi $15, $14, 0x0004 /* extract busy bit */
bne $15, $0, Read56 /* wait for DMA to end */
or $4, $11, $0 /* Init expected data */
or $6, $10, $0 /* R6 = R10 =DMEM addr */
ori $3, $0, 0x0080 /* len of data (bytes) */
ori $7, $0, 0x0001 /* number of spans */
ori $8, $0, 0x0078 /* number of skips */
Chk56: lw $5, 0x0000 ($6) /* read test data */
bne $5, $4, Fail /* verify data */
sub $3, $3, $2 /* decrement counter */
add $4, $4, $2 /* predict next data */
add $6, $6, $2 /* advance DMEM ptr */
bne $3, $0, Chk56 /* check if done */
nop /* bne delay slot */
beq $7, $0, Done56 /* exit if zero span */
ori $3, $0, 0x0080 /* reload len (bytes) */
add $4, $4, $8 /* adjust predict data */
sub $7, $7, $9 /* decrement span cnt */
j Chk56 /* go loop */
Done56:
/****************************************************************
DMA TEST #1.57
****************************************************************/
ori $1, $0, 0x0039 /* R1 = TEST ID */
ori $2, $0, 0x0004 /* R2 = 4 */
ori $9, $0, 0x0001 /* R9 = 1 */
ori $10, $0, 0x07E8 /* R10 = DMEM ADDRESS */
lui $11, 0x0000 /* R11 = DRAM ADDRESS */
ori $11, $11, 0x27F8
lui $12, 0x0800 /* R12 = READ DMA LEN */
ori $12, $12, 0x207F
mtc0 $10, $0 /* write into CP0 reg */
mtc0 $11, $1 /* write into CP0 reg */
mtc0 $12, $2 /* write into CP0 reg */
Read57: mfc0 $14, $4 /* read status reg */
andi $15, $14, 0x0004 /* extract busy bit */
bne $15, $0, Read57 /* wait for DMA to end */
or $4, $11, $0 /* Init expected data */
or $6, $10, $0 /* R6 = R10 =DMEM addr */
ori $3, $0, 0x0080 /* len of data (bytes) */
ori $7, $0, 0x0002 /* number of spans */
ori $8, $0, 0x0080 /* number of skips */
Chk57: lw $5, 0x0000 ($6) /* read test data */
bne $5, $4, Fail /* verify data */
sub $3, $3, $2 /* decrement counter */
add $4, $4, $2 /* predict next data */
add $6, $6, $2 /* advance DMEM ptr */
bne $3, $0, Chk57 /* check if done */
nop /* bne delay slot */
beq $7, $0, Done57 /* exit if zero span */
ori $3, $0, 0x0080 /* reload len (bytes) */
add $4, $4, $8 /* adjust predict data */
sub $7, $7, $9 /* decrement span cnt */
j Chk57 /* go loop */
Done57:
/****************************************************************
DMA TEST #1.58
****************************************************************/
ori $1, $0, 0x003A /* R1 = TEST ID */
ori $2, $0, 0x0004 /* R2 = 4 */
ori $9, $0, 0x0001 /* R9 = 1 */
ori $10, $0, 0x07F0 /* R10 = DMEM ADDRESS */
lui $11, 0x0000 /* R11 = DRAM ADDRESS */
ori $11, $11, 0x2800
lui $12, 0x0880 /* R12 = READ DMA LEN */
ori $12, $12, 0x107F
mtc0 $10, $0 /* write into CP0 reg */
mtc0 $11, $1 /* write into CP0 reg */
mtc0 $12, $2 /* write into CP0 reg */
Read58: mfc0 $14, $4 /* read status reg */
andi $15, $14, 0x0004 /* extract busy bit */
bne $15, $0, Read58 /* wait for DMA to end */
or $4, $11, $0 /* Init expected data */
or $6, $10, $0 /* R6 = R10 =DMEM addr */
ori $3, $0, 0x0080 /* len of data (bytes) */
ori $7, $0, 0x0001 /* number of spans */
ori $8, $0, 0x0088 /* number of skips */
Chk58: lw $5, 0x0000 ($6) /* read test data */
bne $5, $4, Fail /* verify data */
sub $3, $3, $2 /* decrement counter */
add $4, $4, $2 /* predict next data */
add $6, $6, $2 /* advance DMEM ptr */
bne $3, $0, Chk58 /* check if done */
nop /* bne delay slot */
beq $7, $0, Done58 /* exit if zero span */
ori $3, $0, 0x0080 /* reload len (bytes) */
add $4, $4, $8 /* adjust predict data */
sub $7, $7, $9 /* decrement span cnt */
j Chk58 /* go loop */
Done58:
/****************************************************************
DMA TEST #1.59
****************************************************************/
ori $1, $0, 0x003B /* R1 = TEST ID */
ori $2, $0, 0x0004 /* R2 = 4 */
ori $9, $0, 0x0001 /* R9 = 1 */
ori $10, $0, 0x07F8 /* R10 = DMEM ADDRESS */
lui $11, 0x0000 /* R11 = DRAM ADDRESS */
ori $11, $11, 0x2808
lui $12, 0x0900 /* R12 = READ DMA LEN */
ori $12, $12, 0x207F
mtc0 $10, $0 /* write into CP0 reg */
mtc0 $11, $1 /* write into CP0 reg */
mtc0 $12, $2 /* write into CP0 reg */
Read59: mfc0 $14, $4 /* read status reg */
andi $15, $14, 0x0004 /* extract busy bit */
bne $15, $0, Read59 /* wait for DMA to end */
or $4, $11, $0 /* Init expected data */
or $6, $10, $0 /* R6 = R10 =DMEM addr */
ori $3, $0, 0x0080 /* len of data (bytes) */
ori $7, $0, 0x0002 /* number of spans */
ori $8, $0, 0x0090 /* number of skips */
Chk59: lw $5, 0x0000 ($6) /* read test data */
bne $5, $4, Fail /* verify data */
sub $3, $3, $2 /* decrement counter */
add $4, $4, $2 /* predict next data */
add $6, $6, $2 /* advance DMEM ptr */
bne $3, $0, Chk59 /* check if done */
nop /* bne delay slot */
beq $7, $0, Done59 /* exit if zero span */
ori $3, $0, 0x0080 /* reload len (bytes) */
add $4, $4, $8 /* adjust predict data */
sub $7, $7, $9 /* decrement span cnt */
j Chk59 /* go loop */
Done59:
/****************************************************************
DMA TEST #1.60
****************************************************************/
ori $1, $0, 0x003C /* R1 = TEST ID */
ori $2, $0, 0x0004 /* R2 = 4 */
ori $9, $0, 0x0001 /* R9 = 1 */
ori $10, $0, 0x0800 /* R10 = DMEM ADDRESS */
lui $11, 0x0000 /* R11 = DRAM ADDRESS */
ori $11, $11, 0x2F70
lui $12, 0x0980 /* R12 = READ DMA LEN */
ori $12, $12, 0x107F
mtc0 $10, $0 /* write into CP0 reg */
mtc0 $11, $1 /* write into CP0 reg */
mtc0 $12, $2 /* write into CP0 reg */
Read60: mfc0 $14, $4 /* read status reg */
andi $15, $14, 0x0004 /* extract busy bit */
bne $15, $0, Read60 /* wait for DMA to end */
or $4, $11, $0 /* Init expected data */
or $6, $10, $0 /* R6 = R10 =DMEM addr */
ori $3, $0, 0x0080 /* len of data (bytes) */
ori $7, $0, 0x0001 /* number of spans */
ori $8, $0, 0x0098 /* number of skips */
Chk60: lw $5, 0x0000 ($6) /* read test data */
bne $5, $4, Fail /* verify data */
sub $3, $3, $2 /* decrement counter */
add $4, $4, $2 /* predict next data */
add $6, $6, $2 /* advance DMEM ptr */
bne $3, $0, Chk60 /* check if done */
nop /* bne delay slot */
beq $7, $0, Done60 /* exit if zero span */
ori $3, $0, 0x0080 /* reload len (bytes) */
add $4, $4, $8 /* adjust predict data */
sub $7, $7, $9 /* decrement span cnt */
j Chk60 /* go loop */
Done60:
/****************************************************************
Wrap up ...
****************************************************************/
nop
Done: ori $1, $0, 0xFEED /* Test passed */
break
Time: ori $1, $0, 0xDEAD /* Timed-out from DMA */
break
Fail: break