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/************************************************************************
DMA BLOCK WRITE TESTS: File #1
************************************************************************/
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/****************************************************************
DMA TEST #1.13
****************************************************************/
ori $1, $0, 0x000D /* R1 = TEST ID */
ori $2, $0, 0x0004 /* R2 = 4 */
ori $10, $0, 0x07F8 /* R10 = DMEM ADDRESS */
lui $11, 0x0000 /* R11 = DRAM ADDRESS */
ori $11, $11, 0x2808
lui $13, 0xA000 /* R13 = WRITE DMA LEN */
ori $13, $13, 0x100F
/* Prepare DMA write data */
lui $9, 0xFFFF /* ld for bit-wise inv */
ori $9, $9, 0xFFFF
or $6, $10, $0 /* copy DMEM address */
xor $4, $11, $9 /* gen data pattern */
ori $3, $0, 0x0010 /* len of data (bytes) */
ori $7, $0, 0x0001 /* number of spans */
ori $8, $0, 0x0A00 /* number of skips */
Prep13: sw $4, 0x0000 ($6) /* wr pattn into DMEM */
sub $4, $4, $2 /* update data pattern */
sub $3, $3, $2 /* decrement counter */
add $6, $6, $2 /* update DMEM pointer */
bne $3, $0, Prep13 /* done? */
nop /* bne delay slot */
beq $7, $0, Cont13 /* exit loop if 0 span */
ori $3, $0, 0x0010 /* reload length */
sub $4, $4, $8 /* adjust data */
add $7, $7, $9 /* funny decrement */
j Prep13 /* go look */
Cont13:
/* DMA write */
mtc0 $10, $0 /* DMEM ad -> DMA reg */
mtc0 $11, $1 /* DRAM ad -> DMA reg */
mtc0 $13, $3 /* initiate DMA write */
Write13: mfc0 $14, $4 /* read status reg */
andi $15, $14, 0x0004 /* extract busy bit */
bne $15, $0, Write13 /* wait for DMA to end */
/* Mess up DMEM before reading data back */
lui $9, 0x05FF /* load random number */
ori $9, $9, 0x58F2
or $6, $10, $0 /* copy DMEM address */
sw $9, 0x0000 ($6) /* mess-up DMEM */
addi $6, $6, 0x000C /* goto end of DMEM */
sw $9, 0x0000 ($6) /* mess-up DMEM again */
addi $6, $6, 0x0004
sw $9, 0x0000 ($6) /* and again */
addi $6, $6, 0x000C
sw $9, 0x0000 ($6) /* and one last time */
/* DMA read data back */
mtc0 $10, $0 /* DMEM ad -> DMA reg */
mtc0 $11, $1 /* DRAM ad -> DMA reg */
mtc0 $13, $2 /* initiate DMA read */
Read13: mfc0 $14, $4 /* read status reg */
andi $15, $14, 0x0004 /* extract busy bit */
bne $15, $0, Read13 /* wait for DMA to end */
/* Check result */
lui $9, 0xFFFF /* ld for bit-wise inv */
ori $9, $9, 0xFFFF
ori $3, $0, 0x0010 /* len of data (bytes) */
ori $7, $0, 0x0001 /* number of spans */
ori $8, $0, 0x0A00 /* number of skips */
or $4, $11, $0 /* R4 = R11 =DRAM addr */
or $6, $10, $0 /* R6 = R10 =DMEM addr */
Chk13: lw $5, 0x0000 ($6) /* read test data */
xor $5, $5, $9 /* convert data */
bne $5, $4, Fail /* verify data */
nop /* bne delay slot */
sw $5, 0x0000 ($6) /* restore data */
sub $3, $3, $2 /* decrement counter */
add $4, $4, $2 /* predict next data */
add $6, $6, $2 /* advance DMEM ptr */
bne $3, $0, Chk13 /* check if done */
nop /* bne delay slot */
beq $7, $0, Done13 /* exit if zero span */
ori $3, $0, 0x0010 /* reload length */
add $4, $4, $8 /* adjust answer */
add $7, $7, $9 /* decrement span cnt */
j Chk13 /* go loop */
Done13:
/* Clean-up RDRAM */
mtc0 $10, $0 /* DMEM ad -> DMA reg */
mtc0 $11, $1 /* DRAM ad -> DMA reg */
mtc0 $13, $3 /* initiate DMA write */
Cln13: mfc0 $14, $4 /* read status reg */
andi $15, $14, 0x0004 /* extract busy bit */
bne $15, $0, Cln13 /* wait for DMA to end */
nop /* bne delay slot */
/****************************************************************
DMA TEST #1.14
****************************************************************/
ori $1, $0, 0x000E /* R1 = TEST ID */
ori $2, $0, 0x0004 /* R2 = 4 */
ori $10, $0, 0x0800 /* R10 = DMEM ADDRESS */
lui $11, 0x0000 /* R11 = DRAM ADDRESS */
ori $11, $11, 0x2FE8
lui $13, 0x0180 /* R13 = WRITE DMA LEN */
ori $13, $13, 0x200F
/* Prepare DMA write data */
lui $9, 0xFFFF /* ld for bit-wise inv */
ori $9, $9, 0xFFFF
or $6, $10, $0 /* copy DMEM address */
xor $4, $11, $9 /* gen data pattern */
ori $3, $0, 0x0010 /* len of data (bytes) */
ori $7, $0, 0x0002 /* number of spans */
ori $8, $0, 0x0018 /* number of skips */
Prep14: sw $4, 0x0000 ($6) /* wr pattn into DMEM */
sub $4, $4, $2 /* update data pattern */
sub $3, $3, $2 /* decrement counter */
add $6, $6, $2 /* update DMEM pointer */
bne $3, $0, Prep14 /* done? */
nop /* bne delay slot */
beq $7, $0, Cont14 /* exit loop if 0 span */
ori $3, $0, 0x0010 /* reload length */
sub $4, $4, $8 /* adjust data */
add $7, $7, $9 /* funny decrement */
j Prep14 /* go look */
Cont14:
/* DMA write */
mtc0 $10, $0 /* DMEM ad -> DMA reg */
mtc0 $11, $1 /* DRAM ad -> DMA reg */
mtc0 $13, $3 /* initiate DMA write */
Write14: mfc0 $14, $4 /* read status reg */
andi $15, $14, 0x0004 /* extract busy bit */
bne $15, $0, Write14 /* wait for DMA to end */
/* Mess up DMEM before reading data back */
lui $9, 0x282F /* load random number */
ori $9, $9, 0x2EC7
or $6, $10, $0 /* copy DMEM address */
sw $9, 0x0000 ($6) /* mess-up DMEM */
addi $6, $6, 0x000C /* goto end of DMEM */
sw $9, 0x0000 ($6) /* mess-up DMEM again */
addi $6, $6, 0x0004
sw $9, 0x0000 ($6) /* and again */
addi $6, $6, 0x000C
sw $9, 0x0000 ($6) /* and one last time */
/* DMA read data back */
mtc0 $10, $0 /* DMEM ad -> DMA reg */
mtc0 $11, $1 /* DRAM ad -> DMA reg */
mtc0 $13, $2 /* initiate DMA read */
Read14: mfc0 $14, $4 /* read status reg */
andi $15, $14, 0x0004 /* extract busy bit */
bne $15, $0, Read14 /* wait for DMA to end */
/* Check result */
lui $9, 0xFFFF /* ld for bit-wise inv */
ori $9, $9, 0xFFFF
ori $3, $0, 0x0010 /* len of data (bytes) */
ori $7, $0, 0x0002 /* number of spans */
ori $8, $0, 0x0018 /* number of skips */
or $4, $11, $0 /* R4 = R11 =DRAM addr */
or $6, $10, $0 /* R6 = R10 =DMEM addr */
Chk14: lw $5, 0x0000 ($6) /* read test data */
xor $5, $5, $9 /* convert data */
bne $5, $4, Fail /* verify data */
nop /* bne delay slot */
sw $5, 0x0000 ($6) /* restore data */
sub $3, $3, $2 /* decrement counter */
add $4, $4, $2 /* predict next data */
add $6, $6, $2 /* advance DMEM ptr */
bne $3, $0, Chk14 /* check if done */
nop /* bne delay slot */
beq $7, $0, Done14 /* exit if zero span */
ori $3, $0, 0x0010 /* reload length */
add $4, $4, $8 /* adjust answer */
add $7, $7, $9 /* decrement span cnt */
j Chk14 /* go loop */
Done14:
/* Clean-up RDRAM */
mtc0 $10, $0 /* DMEM ad -> DMA reg */
mtc0 $11, $1 /* DRAM ad -> DMA reg */
mtc0 $13, $3 /* initiate DMA write */
Cln14: mfc0 $14, $4 /* read status reg */
andi $15, $14, 0x0004 /* extract busy bit */
bne $15, $0, Cln14 /* wait for DMA to end */
nop /* bne delay slot */
/****************************************************************
DMA TEST #1.15
****************************************************************/
ori $1, $0, 0x000F /* R1 = TEST ID */
ori $2, $0, 0x0004 /* R2 = 4 */
ori $10, $0, 0x0808 /* R10 = DMEM ADDRESS */
lui $11, 0x0000 /* R11 = DRAM ADDRESS */
ori $11, $11, 0x2FF0
lui $13, 0x0280 /* R13 = WRITE DMA LEN */
ori $13, $13, 0x100F
/* Prepare DMA write data */
lui $9, 0xFFFF /* ld for bit-wise inv */
ori $9, $9, 0xFFFF
or $6, $10, $0 /* copy DMEM address */
xor $4, $11, $9 /* gen data pattern */
ori $3, $0, 0x0010 /* len of data (bytes) */
ori $7, $0, 0x0001 /* number of spans */
ori $8, $0, 0x0028 /* number of skips */
Prep15: sw $4, 0x0000 ($6) /* wr pattn into DMEM */
sub $4, $4, $2 /* update data pattern */
sub $3, $3, $2 /* decrement counter */
add $6, $6, $2 /* update DMEM pointer */
bne $3, $0, Prep15 /* done? */
nop /* bne delay slot */
beq $7, $0, Cont15 /* exit loop if 0 span */
ori $3, $0, 0x0010 /* reload length */
sub $4, $4, $8 /* adjust data */
add $7, $7, $9 /* funny decrement */
j Prep15 /* go look */
Cont15:
/* DMA write */
mtc0 $10, $0 /* DMEM ad -> DMA reg */
mtc0 $11, $1 /* DRAM ad -> DMA reg */
mtc0 $13, $3 /* initiate DMA write */
Write15: mfc0 $14, $4 /* read status reg */
andi $15, $14, 0x0004 /* extract busy bit */
bne $15, $0, Write15 /* wait for DMA to end */
/* Mess up DMEM before reading data back */
lui $9, 0x7DB3 /* load random number */
ori $9, $9, 0x127D
or $6, $10, $0 /* copy DMEM address */
sw $9, 0x0000 ($6) /* mess-up DMEM */
addi $6, $6, 0x000C /* goto end of DMEM */
sw $9, 0x0000 ($6) /* mess-up DMEM again */
addi $6, $6, 0x0004
sw $9, 0x0000 ($6) /* and again */
addi $6, $6, 0x000C
sw $9, 0x0000 ($6) /* and one last time */
/* DMA read data back */
mtc0 $10, $0 /* DMEM ad -> DMA reg */
mtc0 $11, $1 /* DRAM ad -> DMA reg */
mtc0 $13, $2 /* initiate DMA read */
Read15: mfc0 $14, $4 /* read status reg */
andi $15, $14, 0x0004 /* extract busy bit */
bne $15, $0, Read15 /* wait for DMA to end */
/* Check result */
lui $9, 0xFFFF /* ld for bit-wise inv */
ori $9, $9, 0xFFFF
ori $3, $0, 0x0010 /* len of data (bytes) */
ori $7, $0, 0x0001 /* number of spans */
ori $8, $0, 0x0028 /* number of skips */
or $4, $11, $0 /* R4 = R11 =DRAM addr */
or $6, $10, $0 /* R6 = R10 =DMEM addr */
Chk15: lw $5, 0x0000 ($6) /* read test data */
xor $5, $5, $9 /* convert data */
bne $5, $4, Fail /* verify data */
nop /* bne delay slot */
sw $5, 0x0000 ($6) /* restore data */
sub $3, $3, $2 /* decrement counter */
add $4, $4, $2 /* predict next data */
add $6, $6, $2 /* advance DMEM ptr */
bne $3, $0, Chk15 /* check if done */
nop /* bne delay slot */
beq $7, $0, Done15 /* exit if zero span */
ori $3, $0, 0x0010 /* reload length */
add $4, $4, $8 /* adjust answer */
add $7, $7, $9 /* decrement span cnt */
j Chk15 /* go loop */
Done15:
/* Clean-up RDRAM */
mtc0 $10, $0 /* DMEM ad -> DMA reg */
mtc0 $11, $1 /* DRAM ad -> DMA reg */
mtc0 $13, $3 /* initiate DMA write */
Cln15: mfc0 $14, $4 /* read status reg */
andi $15, $14, 0x0004 /* extract busy bit */
bne $15, $0, Cln15 /* wait for DMA to end */
nop /* bne delay slot */
/****************************************************************
DMA TEST #1.16
****************************************************************/
ori $1, $0, 0x0010 /* R1 = TEST ID */
ori $2, $0, 0x0004 /* R2 = 4 */
ori $10, $0, 0x0FE8 /* R10 = DMEM ADDRESS */
lui $11, 0x0000 /* R11 = DRAM ADDRESS */
ori $11, $11, 0x2FF8
lui $13, 0xFF80 /* R13 = WRITE DMA LEN */
ori $13, $13, 0x000F
/* Prepare DMA write data */
lui $9, 0xFFFF /* ld for bit-wise inv */
ori $9, $9, 0xFFFF
or $6, $10, $0 /* copy DMEM address */
xor $4, $11, $9 /* gen data pattern */
ori $3, $0, 0x0010 /* len of data (bytes) */
ori $7, $0, 0x0000 /* number of spans */
ori $8, $0, 0x0FF8 /* number of skips */
Prep16: sw $4, 0x0000 ($6) /* wr pattn into DMEM */
sub $4, $4, $2 /* update data pattern */
sub $3, $3, $2 /* decrement counter */
add $6, $6, $2 /* update DMEM pointer */
bne $3, $0, Prep16 /* done? */
nop /* bne delay slot */
beq $7, $0, Cont16 /* exit loop if 0 span */
ori $3, $0, 0x0010 /* reload length */
sub $4, $4, $8 /* adjust data */
add $7, $7, $9 /* funny decrement */
j Prep16 /* go look */
Cont16:
/* DMA write */
mtc0 $10, $0 /* DMEM ad -> DMA reg */
mtc0 $11, $1 /* DRAM ad -> DMA reg */
mtc0 $13, $3 /* initiate DMA write */
Write16: mfc0 $14, $4 /* read status reg */
andi $15, $14, 0x0004 /* extract busy bit */
bne $15, $0, Write16 /* wait for DMA to end */
/* Mess up DMEM before reading data back */
lui $9, 0x2F00 /* load random number */
ori $9, $9, 0x54E8
or $6, $10, $0 /* copy DMEM address */
sw $9, 0x0000 ($6) /* mess-up DMEM */
addi $6, $6, 0x000C /* goto end of DMEM */
sw $9, 0x0000 ($6) /* mess-up DMEM again */
/* DMA read data back */
mtc0 $10, $0 /* DMEM ad -> DMA reg */
mtc0 $11, $1 /* DRAM ad -> DMA reg */
mtc0 $13, $2 /* initiate DMA read */
Read16: mfc0 $14, $4 /* read status reg */
andi $15, $14, 0x0004 /* extract busy bit */
bne $15, $0, Read16 /* wait for DMA to end */
/* Check result */
lui $9, 0xFFFF /* ld for bit-wise inv */
ori $9, $9, 0xFFFF
ori $3, $0, 0x0010 /* len of data (bytes) */
ori $7, $0, 0x0000 /* number of spans */
ori $8, $0, 0x0FF8 /* number of skips */
or $4, $11, $0 /* R4 = R11 =DRAM addr */
or $6, $10, $0 /* R6 = R10 =DMEM addr */
Chk16: lw $5, 0x0000 ($6) /* read test data */
xor $5, $5, $9 /* convert data */
bne $5, $4, Fail /* verify data */
nop /* bne delay slot */
sw $5, 0x0000 ($6) /* restore data */
sub $3, $3, $2 /* decrement counter */
add $4, $4, $2 /* predict next data */
add $6, $6, $2 /* advance DMEM ptr */
bne $3, $0, Chk16 /* check if done */
nop /* bne delay slot */
beq $7, $0, Done16 /* exit if zero span */
ori $3, $0, 0x0010 /* reload length */
add $4, $4, $8 /* adjust answer */
add $7, $7, $9 /* decrement span cnt */
j Chk16 /* go loop */
Done16:
/* Clean-up RDRAM */
mtc0 $10, $0 /* DMEM ad -> DMA reg */
mtc0 $11, $1 /* DRAM ad -> DMA reg */
mtc0 $13, $3 /* initiate DMA write */
Cln16: mfc0 $14, $4 /* read status reg */
andi $15, $14, 0x0004 /* extract busy bit */
bne $15, $0, Cln16 /* wait for DMA to end */
nop /* bne delay slot */
/****************************************************************
DMA TEST #1.17
****************************************************************/
ori $1, $0, 0x0011 /* R1 = TEST ID */
ori $2, $0, 0x0004 /* R2 = 4 */
ori $10, $0, 0x0FF0 /* R10 = DMEM ADDRESS */
lui $11, 0x0000 /* R11 = DRAM ADDRESS */
ori $11, $11, 0x3000
lui $13, 0xFF80 /* R13 = WRITE DMA LEN */
ori $13, $13, 0x000F
/* Prepare DMA write data */
lui $9, 0xFFFF /* ld for bit-wise inv */
ori $9, $9, 0xFFFF
or $6, $10, $0 /* copy DMEM address */
xor $4, $11, $9 /* gen data pattern */
ori $3, $0, 0x0010 /* len of data (bytes) */
ori $7, $0, 0x0000 /* number of spans */
ori $8, $0, 0x0FF8 /* number of skips */
Prep17: sw $4, 0x0000 ($6) /* wr pattn into DMEM */
sub $4, $4, $2 /* update data pattern */
sub $3, $3, $2 /* decrement counter */
add $6, $6, $2 /* update DMEM pointer */
bne $3, $0, Prep17 /* done? */
nop /* bne delay slot */
beq $7, $0, Cont17 /* exit loop if 0 span */
ori $3, $0, 0x0010 /* reload length */
sub $4, $4, $8 /* adjust data */
add $7, $7, $9 /* funny decrement */
j Prep17 /* go look */
Cont17:
/* DMA write */
mtc0 $10, $0 /* DMEM ad -> DMA reg */
mtc0 $11, $1 /* DRAM ad -> DMA reg */
mtc0 $13, $3 /* initiate DMA write */
Write17: mfc0 $14, $4 /* read status reg */
andi $15, $14, 0x0004 /* extract busy bit */
bne $15, $0, Write17 /* wait for DMA to end */
/* Mess up DMEM before reading data back */
lui $9, 0x5074 /* load random number */
ori $9, $9, 0x5A6B
or $6, $10, $0 /* copy DMEM address */
sw $9, 0x0000 ($6) /* mess-up DMEM */
addi $6, $6, 0x000C /* goto end of DMEM */
sw $9, 0x0000 ($6) /* mess-up DMEM again */
/* DMA read data back */
mtc0 $10, $0 /* DMEM ad -> DMA reg */
mtc0 $11, $1 /* DRAM ad -> DMA reg */
mtc0 $13, $2 /* initiate DMA read */
Read17: mfc0 $14, $4 /* read status reg */
andi $15, $14, 0x0004 /* extract busy bit */
bne $15, $0, Read17 /* wait for DMA to end */
/* Check result */
lui $9, 0xFFFF /* ld for bit-wise inv */
ori $9, $9, 0xFFFF
ori $3, $0, 0x0010 /* len of data (bytes) */
ori $7, $0, 0x0000 /* number of spans */
ori $8, $0, 0x0FF8 /* number of skips */
or $4, $11, $0 /* R4 = R11 =DRAM addr */
or $6, $10, $0 /* R6 = R10 =DMEM addr */
Chk17: lw $5, 0x0000 ($6) /* read test data */
xor $5, $5, $9 /* convert data */
bne $5, $4, Fail /* verify data */
nop /* bne delay slot */
sw $5, 0x0000 ($6) /* restore data */
sub $3, $3, $2 /* decrement counter */
add $4, $4, $2 /* predict next data */
add $6, $6, $2 /* advance DMEM ptr */
bne $3, $0, Chk17 /* check if done */
nop /* bne delay slot */
beq $7, $0, Done17 /* exit if zero span */
ori $3, $0, 0x0010 /* reload length */
add $4, $4, $8 /* adjust answer */
add $7, $7, $9 /* decrement span cnt */
j Chk17 /* go loop */
Done17:
/* Clean-up RDRAM */
mtc0 $10, $0 /* DMEM ad -> DMA reg */
mtc0 $11, $1 /* DRAM ad -> DMA reg */
mtc0 $13, $3 /* initiate DMA write */
Cln17: mfc0 $14, $4 /* read status reg */
andi $15, $14, 0x0004 /* extract busy bit */
bne $15, $0, Cln17 /* wait for DMA to end */
nop /* bne delay slot */
/****************************************************************
DMA TEST #1.18
****************************************************************/
ori $1, $0, 0x0012 /* R1 = TEST ID */
ori $2, $0, 0x0004 /* R2 = 4 */
ori $10, $0, 0x0000 /* R10 = DMEM ADDRESS */
lui $11, 0x0000 /* R11 = DRAM ADDRESS */
ori $11, $11, 0x27E0
lui $13, 0x0480 /* R13 = WRITE DMA LEN */
ori $13, $13, 0x1017
/* Prepare DMA write data */
lui $9, 0xFFFF /* ld for bit-wise inv */
ori $9, $9, 0xFFFF
or $6, $10, $0 /* copy DMEM address */
xor $4, $11, $9 /* gen data pattern */
ori $3, $0, 0x0018 /* len of data (bytes) */
ori $7, $0, 0x0001 /* number of spans */
ori $8, $0, 0x0048 /* number of skips */
Prep18: sw $4, 0x0000 ($6) /* wr pattn into DMEM */
sub $4, $4, $2 /* update data pattern */
sub $3, $3, $2 /* decrement counter */
add $6, $6, $2 /* update DMEM pointer */
bne $3, $0, Prep18 /* done? */
nop /* bne delay slot */
beq $7, $0, Cont18 /* exit loop if 0 span */
ori $3, $0, 0x0018 /* reload length */
sub $4, $4, $8 /* adjust data */
add $7, $7, $9 /* funny decrement */
j Prep18 /* go look */
Cont18:
/* DMA write */
mtc0 $10, $0 /* DMEM ad -> DMA reg */
mtc0 $11, $1 /* DRAM ad -> DMA reg */
mtc0 $13, $3 /* initiate DMA write */
Write18: mfc0 $14, $4 /* read status reg */
andi $15, $14, 0x0004 /* extract busy bit */
bne $15, $0, Write18 /* wait for DMA to end */
/* Mess up DMEM before reading data back */
lui $9, 0x2ADD /* load random number */
ori $9, $9, 0x1AEE
or $6, $10, $0 /* copy DMEM address */
sw $9, 0x0000 ($6) /* mess-up DMEM */
addi $6, $6, 0x0014 /* goto end of DMEM */
sw $9, 0x0000 ($6) /* mess-up DMEM again */
addi $6, $6, 0x0004
sw $9, 0x0000 ($6) /* and again */
addi $6, $6, 0x0014
sw $9, 0x0000 ($6) /* and one last time */
/* DMA read data back */
mtc0 $10, $0 /* DMEM ad -> DMA reg */
mtc0 $11, $1 /* DRAM ad -> DMA reg */
mtc0 $13, $2 /* initiate DMA read */
Read18: mfc0 $14, $4 /* read status reg */
andi $15, $14, 0x0004 /* extract busy bit */
bne $15, $0, Read18 /* wait for DMA to end */
/* Check result */
lui $9, 0xFFFF /* ld for bit-wise inv */
ori $9, $9, 0xFFFF
ori $3, $0, 0x0018 /* len of data (bytes) */
ori $7, $0, 0x0001 /* number of spans */
ori $8, $0, 0x0048 /* number of skips */
or $4, $11, $0 /* R4 = R11 =DRAM addr */
or $6, $10, $0 /* R6 = R10 =DMEM addr */
Chk18: lw $5, 0x0000 ($6) /* read test data */
xor $5, $5, $9 /* convert data */
bne $5, $4, Fail /* verify data */
nop /* bne delay slot */
sw $5, 0x0000 ($6) /* restore data */
sub $3, $3, $2 /* decrement counter */
add $4, $4, $2 /* predict next data */
add $6, $6, $2 /* advance DMEM ptr */
bne $3, $0, Chk18 /* check if done */
nop /* bne delay slot */
beq $7, $0, Done18 /* exit if zero span */
ori $3, $0, 0x0018 /* reload length */
add $4, $4, $8 /* adjust answer */
add $7, $7, $9 /* decrement span cnt */
j Chk18 /* go loop */
Done18:
/* Clean-up RDRAM */
mtc0 $10, $0 /* DMEM ad -> DMA reg */
mtc0 $11, $1 /* DRAM ad -> DMA reg */
mtc0 $13, $3 /* initiate DMA write */
Cln18: mfc0 $14, $4 /* read status reg */
andi $15, $14, 0x0004 /* extract busy bit */
bne $15, $0, Cln18 /* wait for DMA to end */
nop /* bne delay slot */
/****************************************************************
DMA TEST #1.19
****************************************************************/
ori $1, $0, 0x0013 /* R1 = TEST ID */
ori $2, $0, 0x0004 /* R2 = 4 */
ori $10, $0, 0x0008 /* R10 = DMEM ADDRESS */
lui $11, 0x0000 /* R11 = DRAM ADDRESS */
ori $11, $11, 0x27E8
lui $13, 0x0880 /* R13 = WRITE DMA LEN */
ori $13, $13, 0x2017
/* Prepare DMA write data */
lui $9, 0xFFFF /* ld for bit-wise inv */
ori $9, $9, 0xFFFF
or $6, $10, $0 /* copy DMEM address */
xor $4, $11, $9 /* gen data pattern */
ori $3, $0, 0x0018 /* len of data (bytes) */
ori $7, $0, 0x0002 /* number of spans */
ori $8, $0, 0x0088 /* number of skips */
Prep19: sw $4, 0x0000 ($6) /* wr pattn into DMEM */
sub $4, $4, $2 /* update data pattern */
sub $3, $3, $2 /* decrement counter */
add $6, $6, $2 /* update DMEM pointer */
bne $3, $0, Prep19 /* done? */
nop /* bne delay slot */
beq $7, $0, Cont19 /* exit loop if 0 span */
ori $3, $0, 0x0018 /* reload length */
sub $4, $4, $8 /* adjust data */
add $7, $7, $9 /* funny decrement */
j Prep19 /* go look */
Cont19:
/* DMA write */
mtc0 $10, $0 /* DMEM ad -> DMA reg */
mtc0 $11, $1 /* DRAM ad -> DMA reg */
mtc0 $13, $3 /* initiate DMA write */
Write19: mfc0 $14, $4 /* read status reg */
andi $15, $14, 0x0004 /* extract busy bit */
bne $15, $0, Write19 /* wait for DMA to end */
/* Mess up DMEM before reading data back */
lui $9, 0x73E6 /* load random number */
ori $9, $9, 0x62E9
or $6, $10, $0 /* copy DMEM address */
sw $9, 0x0000 ($6) /* mess-up DMEM */
addi $6, $6, 0x0014 /* goto end of DMEM */
sw $9, 0x0000 ($6) /* mess-up DMEM again */
addi $6, $6, 0x0004
sw $9, 0x0000 ($6) /* and again */
addi $6, $6, 0x0014
sw $9, 0x0000 ($6) /* and one last time */
/* DMA read data back */
mtc0 $10, $0 /* DMEM ad -> DMA reg */
mtc0 $11, $1 /* DRAM ad -> DMA reg */
mtc0 $13, $2 /* initiate DMA read */
Read19: mfc0 $14, $4 /* read status reg */
andi $15, $14, 0x0004 /* extract busy bit */
bne $15, $0, Read19 /* wait for DMA to end */
/* Check result */
lui $9, 0xFFFF /* ld for bit-wise inv */
ori $9, $9, 0xFFFF
ori $3, $0, 0x0018 /* len of data (bytes) */
ori $7, $0, 0x0002 /* number of spans */
ori $8, $0, 0x0088 /* number of skips */
or $4, $11, $0 /* R4 = R11 =DRAM addr */
or $6, $10, $0 /* R6 = R10 =DMEM addr */
Chk19: lw $5, 0x0000 ($6) /* read test data */
xor $5, $5, $9 /* convert data */
bne $5, $4, Fail /* verify data */
nop /* bne delay slot */
sw $5, 0x0000 ($6) /* restore data */
sub $3, $3, $2 /* decrement counter */
add $4, $4, $2 /* predict next data */
add $6, $6, $2 /* advance DMEM ptr */
bne $3, $0, Chk19 /* check if done */
nop /* bne delay slot */
beq $7, $0, Done19 /* exit if zero span */
ori $3, $0, 0x0018 /* reload length */
add $4, $4, $8 /* adjust answer */
add $7, $7, $9 /* decrement span cnt */
j Chk19 /* go loop */
Done19:
/* Clean-up RDRAM */
mtc0 $10, $0 /* DMEM ad -> DMA reg */
mtc0 $11, $1 /* DRAM ad -> DMA reg */
mtc0 $13, $3 /* initiate DMA write */
Cln19: mfc0 $14, $4 /* read status reg */
andi $15, $14, 0x0004 /* extract busy bit */
bne $15, $0, Cln19 /* wait for DMA to end */
nop /* bne delay slot */
/****************************************************************
DMA TEST #1.20
****************************************************************/
ori $1, $0, 0x0014 /* R1 = TEST ID */
ori $2, $0, 0x0004 /* R2 = 4 */
ori $10, $0, 0x07E0 /* R10 = DMEM ADDRESS */
lui $11, 0x0000 /* R11 = DRAM ADDRESS */
ori $11, $11, 0x27F0
lui $13, 0x1080 /* R13 = WRITE DMA LEN */
ori $13, $13, 0x1017
/* Prepare DMA write data */
lui $9, 0xFFFF /* ld for bit-wise inv */
ori $9, $9, 0xFFFF
or $6, $10, $0 /* copy DMEM address */
xor $4, $11, $9 /* gen data pattern */
ori $3, $0, 0x0018 /* len of data (bytes) */
ori $7, $0, 0x0001 /* number of spans */
ori $8, $0, 0x0108 /* number of skips */
Prep20: sw $4, 0x0000 ($6) /* wr pattn into DMEM */
sub $4, $4, $2 /* update data pattern */
sub $3, $3, $2 /* decrement counter */
add $6, $6, $2 /* update DMEM pointer */
bne $3, $0, Prep20 /* done? */
nop /* bne delay slot */
beq $7, $0, Cont20 /* exit loop if 0 span */
ori $3, $0, 0x0018 /* reload length */
sub $4, $4, $8 /* adjust data */
add $7, $7, $9 /* funny decrement */
j Prep20 /* go look */
Cont20:
/* DMA write */
mtc0 $10, $0 /* DMEM ad -> DMA reg */
mtc0 $11, $1 /* DRAM ad -> DMA reg */
mtc0 $13, $3 /* initiate DMA write */
Write20: mfc0 $14, $4 /* read status reg */
andi $15, $14, 0x0004 /* extract busy bit */
bne $15, $0, Write20 /* wait for DMA to end */
/* Mess up DMEM before reading data back */
lui $9, 0x4BE8 /* load random number */
ori $9, $9, 0x4995
or $6, $10, $0 /* copy DMEM address */
sw $9, 0x0000 ($6) /* mess-up DMEM */
addi $6, $6, 0x0014 /* goto end of DMEM */
sw $9, 0x0000 ($6) /* mess-up DMEM again */
addi $6, $6, 0x0004
sw $9, 0x0000 ($6) /* and again */
addi $6, $6, 0x0014
sw $9, 0x0000 ($6) /* and one last time */
/* DMA read data back */
mtc0 $10, $0 /* DMEM ad -> DMA reg */
mtc0 $11, $1 /* DRAM ad -> DMA reg */
mtc0 $13, $2 /* initiate DMA read */
Read20: mfc0 $14, $4 /* read status reg */
andi $15, $14, 0x0004 /* extract busy bit */
bne $15, $0, Read20 /* wait for DMA to end */
/* Check result */
lui $9, 0xFFFF /* ld for bit-wise inv */
ori $9, $9, 0xFFFF
ori $3, $0, 0x0018 /* len of data (bytes) */
ori $7, $0, 0x0001 /* number of spans */
ori $8, $0, 0x0108 /* number of skips */
or $4, $11, $0 /* R4 = R11 =DRAM addr */
or $6, $10, $0 /* R6 = R10 =DMEM addr */
Chk20: lw $5, 0x0000 ($6) /* read test data */
xor $5, $5, $9 /* convert data */
bne $5, $4, Fail /* verify data */
nop /* bne delay slot */
sw $5, 0x0000 ($6) /* restore data */
sub $3, $3, $2 /* decrement counter */
add $4, $4, $2 /* predict next data */
add $6, $6, $2 /* advance DMEM ptr */
bne $3, $0, Chk20 /* check if done */
nop /* bne delay slot */
beq $7, $0, Done20 /* exit if zero span */
ori $3, $0, 0x0018 /* reload length */
add $4, $4, $8 /* adjust answer */
add $7, $7, $9 /* decrement span cnt */
j Chk20 /* go loop */
Done20:
/* Clean-up RDRAM */
mtc0 $10, $0 /* DMEM ad -> DMA reg */
mtc0 $11, $1 /* DRAM ad -> DMA reg */
mtc0 $13, $3 /* initiate DMA write */
Cln20: mfc0 $14, $4 /* read status reg */
andi $15, $14, 0x0004 /* extract busy bit */
bne $15, $0, Cln20 /* wait for DMA to end */
nop /* bne delay slot */
/****************************************************************
DMA TEST #1.21
****************************************************************/
ori $1, $0, 0x0015 /* R1 = TEST ID */
ori $2, $0, 0x0004 /* R2 = 4 */
ori $10, $0, 0x07E8 /* R10 = DMEM ADDRESS */
lui $11, 0x0000 /* R11 = DRAM ADDRESS */
ori $11, $11, 0x27F8
lui $13, 0x2080 /* R13 = WRITE DMA LEN */
ori $13, $13, 0x2017
/* Prepare DMA write data */
lui $9, 0xFFFF /* ld for bit-wise inv */
ori $9, $9, 0xFFFF
or $6, $10, $0 /* copy DMEM address */
xor $4, $11, $9 /* gen data pattern */
ori $3, $0, 0x0018 /* len of data (bytes) */
ori $7, $0, 0x0002 /* number of spans */
ori $8, $0, 0x0208 /* number of skips */
Prep21: sw $4, 0x0000 ($6) /* wr pattn into DMEM */
sub $4, $4, $2 /* update data pattern */
sub $3, $3, $2 /* decrement counter */
add $6, $6, $2 /* update DMEM pointer */
bne $3, $0, Prep21 /* done? */
nop /* bne delay slot */
beq $7, $0, Cont21 /* exit loop if 0 span */
ori $3, $0, 0x0018 /* reload length */
sub $4, $4, $8 /* adjust data */
add $7, $7, $9 /* funny decrement */
j Prep21 /* go look */
Cont21:
/* DMA write */
mtc0 $10, $0 /* DMEM ad -> DMA reg */
mtc0 $11, $1 /* DRAM ad -> DMA reg */
mtc0 $13, $3 /* initiate DMA write */
Write21: mfc0 $14, $4 /* read status reg */
andi $15, $14, 0x0004 /* extract busy bit */
bne $15, $0, Write21 /* wait for DMA to end */
/* Mess up DMEM before reading data back */
lui $9, 0x3F54 /* load random number */
ori $9, $9, 0x6A16
or $6, $10, $0 /* copy DMEM address */
sw $9, 0x0000 ($6) /* mess-up DMEM */
addi $6, $6, 0x0014 /* goto end of DMEM */
sw $9, 0x0000 ($6) /* mess-up DMEM again */
addi $6, $6, 0x0004
sw $9, 0x0000 ($6) /* and again */
addi $6, $6, 0x0014
sw $9, 0x0000 ($6) /* and one last time */
/* DMA read data back */
mtc0 $10, $0 /* DMEM ad -> DMA reg */
mtc0 $11, $1 /* DRAM ad -> DMA reg */
mtc0 $13, $2 /* initiate DMA read */
Read21: mfc0 $14, $4 /* read status reg */
andi $15, $14, 0x0004 /* extract busy bit */
bne $15, $0, Read21 /* wait for DMA to end */
/* Check result */
lui $9, 0xFFFF /* ld for bit-wise inv */
ori $9, $9, 0xFFFF
ori $3, $0, 0x0018 /* len of data (bytes) */
ori $7, $0, 0x0002 /* number of spans */
ori $8, $0, 0x0208 /* number of skips */
or $4, $11, $0 /* R4 = R11 =DRAM addr */
or $6, $10, $0 /* R6 = R10 =DMEM addr */
Chk21: lw $5, 0x0000 ($6) /* read test data */
xor $5, $5, $9 /* convert data */
bne $5, $4, Fail /* verify data */
nop /* bne delay slot */
sw $5, 0x0000 ($6) /* restore data */
sub $3, $3, $2 /* decrement counter */
add $4, $4, $2 /* predict next data */
add $6, $6, $2 /* advance DMEM ptr */
bne $3, $0, Chk21 /* check if done */
nop /* bne delay slot */
beq $7, $0, Done21 /* exit if zero span */
ori $3, $0, 0x0018 /* reload length */
add $4, $4, $8 /* adjust answer */
add $7, $7, $9 /* decrement span cnt */
j Chk21 /* go loop */
Done21:
/* Clean-up RDRAM */
mtc0 $10, $0 /* DMEM ad -> DMA reg */
mtc0 $11, $1 /* DRAM ad -> DMA reg */
mtc0 $13, $3 /* initiate DMA write */
Cln21: mfc0 $14, $4 /* read status reg */
andi $15, $14, 0x0004 /* extract busy bit */
bne $15, $0, Cln21 /* wait for DMA to end */
nop /* bne delay slot */
/****************************************************************
DMA TEST #1.22
****************************************************************/
ori $1, $0, 0x0016 /* R1 = TEST ID */
ori $2, $0, 0x0004 /* R2 = 4 */
ori $10, $0, 0x07F0 /* R10 = DMEM ADDRESS */
lui $11, 0x0000 /* R11 = DRAM ADDRESS */
ori $11, $11, 0x2800
lui $13, 0x4080 /* R13 = WRITE DMA LEN */
ori $13, $13, 0x1017
/* Prepare DMA write data */
lui $9, 0xFFFF /* ld for bit-wise inv */
ori $9, $9, 0xFFFF
or $6, $10, $0 /* copy DMEM address */
xor $4, $11, $9 /* gen data pattern */
ori $3, $0, 0x0018 /* len of data (bytes) */
ori $7, $0, 0x0001 /* number of spans */
ori $8, $0, 0x0408 /* number of skips */
Prep22: sw $4, 0x0000 ($6) /* wr pattn into DMEM */
sub $4, $4, $2 /* update data pattern */
sub $3, $3, $2 /* decrement counter */
add $6, $6, $2 /* update DMEM pointer */
bne $3, $0, Prep22 /* done? */
nop /* bne delay slot */
beq $7, $0, Cont22 /* exit loop if 0 span */
ori $3, $0, 0x0018 /* reload length */
sub $4, $4, $8 /* adjust data */
add $7, $7, $9 /* funny decrement */
j Prep22 /* go look */
Cont22:
/* DMA write */
mtc0 $10, $0 /* DMEM ad -> DMA reg */
mtc0 $11, $1 /* DRAM ad -> DMA reg */
mtc0 $13, $3 /* initiate DMA write */
Write22: mfc0 $14, $4 /* read status reg */
andi $15, $14, 0x0004 /* extract busy bit */
bne $15, $0, Write22 /* wait for DMA to end */
/* Mess up DMEM before reading data back */
lui $9, 0x00B2 /* load random number */
ori $9, $9, 0x7D45
or $6, $10, $0 /* copy DMEM address */
sw $9, 0x0000 ($6) /* mess-up DMEM */
addi $6, $6, 0x0014 /* goto end of DMEM */
sw $9, 0x0000 ($6) /* mess-up DMEM again */
addi $6, $6, 0x0004
sw $9, 0x0000 ($6) /* and again */
addi $6, $6, 0x0014
sw $9, 0x0000 ($6) /* and one last time */
/* DMA read data back */
mtc0 $10, $0 /* DMEM ad -> DMA reg */
mtc0 $11, $1 /* DRAM ad -> DMA reg */
mtc0 $13, $2 /* initiate DMA read */
Read22: mfc0 $14, $4 /* read status reg */
andi $15, $14, 0x0004 /* extract busy bit */
bne $15, $0, Read22 /* wait for DMA to end */
/* Check result */
lui $9, 0xFFFF /* ld for bit-wise inv */
ori $9, $9, 0xFFFF
ori $3, $0, 0x0018 /* len of data (bytes) */
ori $7, $0, 0x0001 /* number of spans */
ori $8, $0, 0x0408 /* number of skips */
or $4, $11, $0 /* R4 = R11 =DRAM addr */
or $6, $10, $0 /* R6 = R10 =DMEM addr */
Chk22: lw $5, 0x0000 ($6) /* read test data */
xor $5, $5, $9 /* convert data */
bne $5, $4, Fail /* verify data */
nop /* bne delay slot */
sw $5, 0x0000 ($6) /* restore data */
sub $3, $3, $2 /* decrement counter */
add $4, $4, $2 /* predict next data */
add $6, $6, $2 /* advance DMEM ptr */
bne $3, $0, Chk22 /* check if done */
nop /* bne delay slot */
beq $7, $0, Done22 /* exit if zero span */
ori $3, $0, 0x0018 /* reload length */
add $4, $4, $8 /* adjust answer */
add $7, $7, $9 /* decrement span cnt */
j Chk22 /* go loop */
Done22:
/* Clean-up RDRAM */
mtc0 $10, $0 /* DMEM ad -> DMA reg */
mtc0 $11, $1 /* DRAM ad -> DMA reg */
mtc0 $13, $3 /* initiate DMA write */
Cln22: mfc0 $14, $4 /* read status reg */
andi $15, $14, 0x0004 /* extract busy bit */
bne $15, $0, Cln22 /* wait for DMA to end */
nop /* bne delay slot */
/****************************************************************
DMA TEST #1.23
****************************************************************/
ori $1, $0, 0x0017 /* R1 = TEST ID */
ori $2, $0, 0x0004 /* R2 = 4 */
ori $10, $0, 0x07F8 /* R10 = DMEM ADDRESS */
lui $11, 0x0000 /* R11 = DRAM ADDRESS */
ori $11, $11, 0x2808
lui $13, 0x8080 /* R13 = WRITE DMA LEN */
ori $13, $13, 0x2017
/* Prepare DMA write data */
lui $9, 0xFFFF /* ld for bit-wise inv */
ori $9, $9, 0xFFFF
or $6, $10, $0 /* copy DMEM address */
xor $4, $11, $9 /* gen data pattern */
ori $3, $0, 0x0018 /* len of data (bytes) */
ori $7, $0, 0x0002 /* number of spans */
ori $8, $0, 0x0808 /* number of skips */
Prep23: sw $4, 0x0000 ($6) /* wr pattn into DMEM */
sub $4, $4, $2 /* update data pattern */
sub $3, $3, $2 /* decrement counter */
add $6, $6, $2 /* update DMEM pointer */
bne $3, $0, Prep23 /* done? */
nop /* bne delay slot */
beq $7, $0, Cont23 /* exit loop if 0 span */
ori $3, $0, 0x0018 /* reload length */
sub $4, $4, $8 /* adjust data */
add $7, $7, $9 /* funny decrement */
j Prep23 /* go look */
Cont23:
/* DMA write */
mtc0 $10, $0 /* DMEM ad -> DMA reg */
mtc0 $11, $1 /* DRAM ad -> DMA reg */
mtc0 $13, $3 /* initiate DMA write */
Write23: mfc0 $14, $4 /* read status reg */
andi $15, $14, 0x0004 /* extract busy bit */
bne $15, $0, Write23 /* wait for DMA to end */
/* Mess up DMEM before reading data back */
lui $9, 0x44EF /* load random number */
ori $9, $9, 0x675F
or $6, $10, $0 /* copy DMEM address */
sw $9, 0x0000 ($6) /* mess-up DMEM */
addi $6, $6, 0x0014 /* goto end of DMEM */
sw $9, 0x0000 ($6) /* mess-up DMEM again */
addi $6, $6, 0x0004
sw $9, 0x0000 ($6) /* and again */
addi $6, $6, 0x0014
sw $9, 0x0000 ($6) /* and one last time */
/* DMA read data back */
mtc0 $10, $0 /* DMEM ad -> DMA reg */
mtc0 $11, $1 /* DRAM ad -> DMA reg */
mtc0 $13, $2 /* initiate DMA read */
Read23: mfc0 $14, $4 /* read status reg */
andi $15, $14, 0x0004 /* extract busy bit */
bne $15, $0, Read23 /* wait for DMA to end */
/* Check result */
lui $9, 0xFFFF /* ld for bit-wise inv */
ori $9, $9, 0xFFFF
ori $3, $0, 0x0018 /* len of data (bytes) */
ori $7, $0, 0x0002 /* number of spans */
ori $8, $0, 0x0808 /* number of skips */
or $4, $11, $0 /* R4 = R11 =DRAM addr */
or $6, $10, $0 /* R6 = R10 =DMEM addr */
Chk23: lw $5, 0x0000 ($6) /* read test data */
xor $5, $5, $9 /* convert data */
bne $5, $4, Fail /* verify data */
nop /* bne delay slot */
sw $5, 0x0000 ($6) /* restore data */
sub $3, $3, $2 /* decrement counter */
add $4, $4, $2 /* predict next data */
add $6, $6, $2 /* advance DMEM ptr */
bne $3, $0, Chk23 /* check if done */
nop /* bne delay slot */
beq $7, $0, Done23 /* exit if zero span */
ori $3, $0, 0x0018 /* reload length */
add $4, $4, $8 /* adjust answer */
add $7, $7, $9 /* decrement span cnt */
j Chk23 /* go loop */
Done23:
/* Clean-up RDRAM */
mtc0 $10, $0 /* DMEM ad -> DMA reg */
mtc0 $11, $1 /* DRAM ad -> DMA reg */
mtc0 $13, $3 /* initiate DMA write */
Cln23: mfc0 $14, $4 /* read status reg */
andi $15, $14, 0x0004 /* extract busy bit */
bne $15, $0, Cln23 /* wait for DMA to end */
nop /* bne delay slot */
/****************************************************************
DMA TEST #1.24
****************************************************************/
ori $1, $0, 0x0018 /* R1 = TEST ID */
ori $2, $0, 0x0004 /* R2 = 4 */
ori $10, $0, 0x0800 /* R10 = DMEM ADDRESS */
lui $11, 0x0000 /* R11 = DRAM ADDRESS */
ori $11, $11, 0x2FE8
lui $13, 0x0300 /* R13 = WRITE DMA LEN */
ori $13, $13, 0x1017
/* Prepare DMA write data */
lui $9, 0xFFFF /* ld for bit-wise inv */
ori $9, $9, 0xFFFF
or $6, $10, $0 /* copy DMEM address */
xor $4, $11, $9 /* gen data pattern */
ori $3, $0, 0x0018 /* len of data (bytes) */
ori $7, $0, 0x0001 /* number of spans */
ori $8, $0, 0x0030 /* number of skips */
Prep24: sw $4, 0x0000 ($6) /* wr pattn into DMEM */
sub $4, $4, $2 /* update data pattern */
sub $3, $3, $2 /* decrement counter */
add $6, $6, $2 /* update DMEM pointer */
bne $3, $0, Prep24 /* done? */
nop /* bne delay slot */
beq $7, $0, Cont24 /* exit loop if 0 span */
ori $3, $0, 0x0018 /* reload length */
sub $4, $4, $8 /* adjust data */
add $7, $7, $9 /* funny decrement */
j Prep24 /* go look */
Cont24:
/* DMA write */
mtc0 $10, $0 /* DMEM ad -> DMA reg */
mtc0 $11, $1 /* DRAM ad -> DMA reg */
mtc0 $13, $3 /* initiate DMA write */
Write24: mfc0 $14, $4 /* read status reg */
andi $15, $14, 0x0004 /* extract busy bit */
bne $15, $0, Write24 /* wait for DMA to end */
/* Mess up DMEM before reading data back */
lui $9, 0x4E66 /* load random number */
ori $9, $9, 0x18C6
or $6, $10, $0 /* copy DMEM address */
sw $9, 0x0000 ($6) /* mess-up DMEM */
addi $6, $6, 0x0014 /* goto end of DMEM */
sw $9, 0x0000 ($6) /* mess-up DMEM again */
addi $6, $6, 0x0004
sw $9, 0x0000 ($6) /* and again */
addi $6, $6, 0x0014
sw $9, 0x0000 ($6) /* and one last time */
/* DMA read data back */
mtc0 $10, $0 /* DMEM ad -> DMA reg */
mtc0 $11, $1 /* DRAM ad -> DMA reg */
mtc0 $13, $2 /* initiate DMA read */
Read24: mfc0 $14, $4 /* read status reg */
andi $15, $14, 0x0004 /* extract busy bit */
bne $15, $0, Read24 /* wait for DMA to end */
/* Check result */
lui $9, 0xFFFF /* ld for bit-wise inv */
ori $9, $9, 0xFFFF
ori $3, $0, 0x0018 /* len of data (bytes) */
ori $7, $0, 0x0001 /* number of spans */
ori $8, $0, 0x0030 /* number of skips */
or $4, $11, $0 /* R4 = R11 =DRAM addr */
or $6, $10, $0 /* R6 = R10 =DMEM addr */
Chk24: lw $5, 0x0000 ($6) /* read test data */
xor $5, $5, $9 /* convert data */
bne $5, $4, Fail /* verify data */
nop /* bne delay slot */
sw $5, 0x0000 ($6) /* restore data */
sub $3, $3, $2 /* decrement counter */
add $4, $4, $2 /* predict next data */
add $6, $6, $2 /* advance DMEM ptr */
bne $3, $0, Chk24 /* check if done */
nop /* bne delay slot */
beq $7, $0, Done24 /* exit if zero span */
ori $3, $0, 0x0018 /* reload length */
add $4, $4, $8 /* adjust answer */
add $7, $7, $9 /* decrement span cnt */
j Chk24 /* go loop */
Done24:
/* Clean-up RDRAM */
mtc0 $10, $0 /* DMEM ad -> DMA reg */
mtc0 $11, $1 /* DRAM ad -> DMA reg */
mtc0 $13, $3 /* initiate DMA write */
Cln24: mfc0 $14, $4 /* read status reg */
andi $15, $14, 0x0004 /* extract busy bit */
bne $15, $0, Cln24 /* wait for DMA to end */
nop /* bne delay slot */
/****************************************************************
Wrap up ...
****************************************************************/
nop
Done: ori $1, $0, 0xFEED /* Test passed */
break
Time: ori $1, $0, 0xDEAD /* Timed-out from DMA */
break
Fail: break