#!/bin/csh

./randdata 31 > init_regs
mv dmem test.regs

./randdata 31 4 > init_vregs
mv dmem test.vreg

./randdata 1024 > /dev/null
mv dmem test.dat

./randinst $1 > test.lst
mv insts test.out

#
# At this point we have:
#
#  C-sim File	Verilog File	File Purpose
#
#   test.lst	 test.lst	Execution Listing File
#
#   test.out	 test.out	IMEM initial Value
#
#   test.dat	 test.dat	DMEM initial Value
#
#   init_regs	 test.regs	Register File initial Value
#
#

./rsp -tRz < go |& sed -e "s/^rsp > //" | egrep "^0x0" > trace.out
sed 's/://' trace.out | awk '{print $3}' | tee pcs | nper | tail -1 | awk '{ print $10}' >> test.cnt

# ( echo ibase=16 ; tr "[a-z]" "[A-Z]" < pcs | cut -c8-10 ) | bc > dpcs

#
# At this point we also have:
#
#  C-sim File	Verilog File	File Purpose
#
#   trace.out	 trace_out	Execution Results
#
#   test.cnt	 		Simulation count
#

cp trace_out test.ctrace
echo -n "NC  " >> test.ctrace
@ cnt = `tail -1 test.cnt`

( echo obase=16 ; echo $cnt ) | bc | tr "[A-Z]" "[a-z]" >> test.ctrace