io_pad_test.v
1.28 KB
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
`timescale 1ns / 10ps
module io_pad_test;
`define CLK reality.rcp_0.clock
initial
begin
#16
reality.r4200b_0.test_selected = 1;
wait(`SYSTEM_READY);
repeat (4) @(posedge `CLK);
reality.r4200b_0.config_rdram;
// RDRAM
repeat (4) @(posedge `CLK);
reality.r4200b_0.write_word('h0, 3, 'h12345678);
reality.r4200b_0.data[0] = 'h0;
reality.r4200b_0.read_word('h0, 3);
if (reality.r4200b_0.data[0]!=='h12345678) $display ("RRDATA from RDRAM MISCOMPARED: FAILED");
// pi
repeat (4) @(posedge `CLK);
reality.r4200b_0.write_word('h900_0000, 3, 'h5555aaaa);
reality.r4200b_0.data[0] = 'h0;
reality.r4200b_0.read_word('h900_0000, 3);
if (reality.r4200b_0.data[0]!=='h5555aaaa) $display ("RRDATA from RWROM MISCOMPARED: FAILED");
// si
repeat (4) @(posedge `CLK);
reality.r4200b_0.write_word('h1fc0_07c0, 3, 'habcdef01);
reality.r4200b_0.data[0] = 'h0;
reality.r4200b_0.read_word('h1fc0_07c0, 3);
if (reality.r4200b_0.data[0]!=='habcdef01) $display ("RRDATA from PIF MISCOMPARED: FAILED");
// interrupt
repeat (4) @(posedge `CLK);
reality.r4200b_0.write_word('h0430_000c, 3, 'h2);
fork
reality.r4200b_0.write_word('h0404_0010, 3, 'h10);
wait (reality.rcp_0.int_pad === 1'b0);
join
fork
reality.r4200b_0.write_word('h0404_0010, 3, 'h8);
wait (reality.rcp_0.int_pad === 1'b1);
join
$finish;
end
endmodule