ram_bist_go.v
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`timescale 1ns / 10ps
module rcp_misc_test;
reg imem_bist_done;
reg tmem_bist_done;
reg [6:0] imem_bist_status;
reg [10:0] tmem_bist_status;
`define IMEM_BIST_ADDR 'h0408_0004
`define TMEM_BIST_ADDR 'h0420_0000
`define CLK reality.rcp_0.clock
//initial $dumpvars;
initial
begin
#16
reality.r4200b_0.test_selected = 1;
wait(`SYSTEM_READY);
repeat (4) @(posedge `CLK);
/******************************************************
* clear bist
******************************************************/
reality.r4200b_0.write_word(`IMEM_BIST_ADDR, 3, 'h4);
reality.r4200b_0.write_word(`TMEM_BIST_ADDR, 3, 'h4);
/******************************************************
* set GO
******************************************************/
$display ($time, "\n\nSetting GO ");
reality.r4200b_0.write_word(`IMEM_BIST_ADDR, 3, 'h2);
reality.r4200b_0.write_word(`TMEM_BIST_ADDR, 3, 'h2);
reality.r4200b_0.data[0] = 'h0;
imem_bist_done = 0;
tmem_bist_done = 0;
while (imem_bist_done === 1'b0 || tmem_bist_done === 1'b0)
begin
repeat (1000) @(posedge `CLK);
reality.r4200b_0.read_word(`IMEM_BIST_ADDR, 3);
imem_bist_done = reality.r4200b_0.data[0] >> 2;
imem_bist_status = reality.r4200b_0.data[0];
reality.r4200b_0.read_word(`TMEM_BIST_ADDR, 3);
tmem_bist_done = reality.r4200b_0.data[0] >> 2;
tmem_bist_status = reality.r4200b_0.data[0];
$display ($time, " IMEM BIST status = %h", imem_bist_status);
$display ($time, " TMEM BIST status = %h", tmem_bist_status);
if (!imem_bist_done && imem_bist_status !== 'h2)
begin
$display($time," ERROR: imem bist status is wrong");
$finish;
end
if (!tmem_bist_done && tmem_bist_status !== 'h2)
begin
$display($time," ERROR: tmem bist status is wrong");
$finish;
end
end
if (imem_bist_status !== 'h6)
begin
$display($time," ERROR: imem bist status is wrong");
$finish;
end
if (tmem_bist_status !== 'h6)
begin
$display($time," ERROR: tmem bist status is wrong");
$finish;
end
$finish;
end
endmodule