rsp_regression.makefile
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#!smake
#
# This makefile has rules for making both the executables
# which make up the simulator, and for running test cases.
#
# $Revision: 1.8 $
#
COMMONPREF=bcp
PRDEPTH = $(ROOT)/PR
REGRESSION = $(PRDEPTH)/rspsim/vuregre/regression2
RSPDIR = $(PRDEPTH)/hw2/chip/bcp/rsp/src
VCSDIR = /ecad/vcs/intel_i686_linux_2.2
include $(PRDEPTH)/PRdefs
#
# Directory to store verilog output files (simv, simv.daidir, csrc)
# All *.o and *.c files will be placed in $(SIMVDIR)
# User can overide this variable on make command line (i.e. make SIMVDIR=/tmp)
#
SIMVDIR = ./designc
#
# Tools
#
SIMV = LD_LIBRARY_PATH=$(VCSDIR)/lib $(SIMVDIR)/simv -q
#
# Directories
#
#
# C Sources
#
# Header file Directories
#
LCINCS =
GCINCS =
#
# Compiler options
#
OPTIMIZER = -g
LCOPTS = -fullwarn
#
# Verilog compiler options
#
# override GVCSOPTS
#
GVCSOPTS = -l vcs.log -M -Mupdate \
-CC "-Wab,-big_got -Wab,-dwalign" -V \
VSYNPATH = $(PRDEPTH)/hw2/chip/bcp/rsp/vsyn
GATE_FILES = \
$(VSYNPATH)/divctl.vsyn \
$(VSYNPATH)/io_cmd_dma.vsyn \
$(VSYNPATH)/io_mem_dma.vsyn \
$(VSYNPATH)/ls.vsyn \
$(VSYNPATH)/rspbusses.vsyn \
$(VSYNPATH)/su.vsyn \
$(VSYNPATH)/vu.vsyn \
$(VSYNPATH)/vusl.vsyn \
LVCSOPTS = -y . \
-P $(PRDEPTH)/lib/libbcppli/bcppli.tab $(PRDEPTH)/lib/libbcppli/libbcppli.a \
-y $(PRDEPTH)/hw2/chip/bcp/su/src \
-y $(PRDEPTH)/hw2/chip/bcp/su/fixes \
-y $(PRDEPTH)/hw2/chip/bcp/vu/src \
-y $(PRDEPTH)/hw2/chip/bcp/ls/src \
-y $(PRDEPTH)/hw2/chip/bcp/sb/src \
-y $(PRDEPTH)/hw2/chip/bcp/dm/src \
-y $(PRDEPTH)/hw2/chip/bcp/rsp/src \
-y $(PRDEPTH)/hw2/chip/bcp/io/src \
-y $(PRDEPTH)/hw2/chip/lib/verilog/ram \
-y $(PRDEPTH)/hw2/chip/lib/verilog/dp \
-y $(PRDEPTH)/hw2/chip/lib/verilog/stdcell \
-y $(PRDEPTH)/hw2/chip/lib/verilog/user \
-y $(PRDEPTH)/hw2/chip/lib/verilog/nec \
-y $(PRDEPTH)/hw2/chip/lib/verilog/dbus \
-y $(PRDEPTH)/hw2/chip/lib/verilog/cbus \
-y $(PRDEPTH)/hw2/chip/lib/verilog/nec.15/memories \
-y $(PRDEPTH)/hw2/chip/lib/verilog/jlib \
+libext+.v+.vmd+ \
+incdir+$(PRDEPTH)/hw2/chip/bcp/rsp/lib \
+incdir+$(PRDEPTH)/hw2/chip/bcp/su/src \
+incdir+$(PRDEPTH)/hw2/chip/bcp/vu/src \
+incdir+$(PRDEPTH)/hw2/chip/bcp/inc \
+incdir+$(PRDEPTH)/hw2/chip/include \
+incdir+$(REGRESSION) \
-Mdir=$(SIMVDIR) \
+define+NEC_RTL_SIM +notimingchecks
# Default Targets
#
TESTS = simv
default install: $(TESTS)
$(COMMONTARGS): $(COMMONPREF)$$@
$(SUBDIRS_MAKERULE)
#
# SGI/Project Reality Common Rules
#
include $(PRDEPTH)/PRrules
#
# Compile Verilog processes
#
simv: $(RSPDIR)/rspWrap_regression.v $(_FORCE)
# VCS_RUNTIME=$(VCSDIR)/lib/libvcs.a
$(VCS) $(VCSOPTS) -o $(SIMVDIR)/$@ \
$(RSPDIR)/rspWrap_regression.v \
$(REGRESSION)/rsp_ctrace.v \
$(REGRESSION)/rsp_random_dma.v \
./rsp_tests.v \
simv_gate: $(RSPDIR)/rspWrap_regression.v $(_FORCE)
# VCS_RUNTIME=$(VCSDIR)/lib/libvcs.so
$(VCS) +define+RSP_GATE $(VCSOPTS) -o $(SIMVDIR)/$@ \
$(RSPDIR)/rspWrap_regression.v \
$(GATE_FILES) \
$(REGRESSION)/rsp_ctrace.v \
$(REGRESSION)/rsp_random_dma.v \
./rsp_tests.v