ev5_ipr.h
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/*
* Copyright (C) 1998 by the Board of Trustees
* of Leland Stanford Junior University.
* Copyright (C) 1998 Digital Equipment Corporation
*
* This file is part of the SimOS distribution.
* See LICENSE file for terms of the license.
*
*/
#ifndef EV5_IPR_H
#define EV5_IPR_H
/* PAL Dispatch Addresses ****************************************************/
#define TRAP_RESET 0x0001
#define TRAP_MCHK 0x0401
#define TRAP_ARITH 0x0501
#define TRAP_INTERRUPT 0x0101
#define TRAP_NDTB_MISS 0x0201 /* basic D-tb miss */
#define TRAP_PDTB_MISS 0x0281 /* nestetd D-tb miss */
#define TRAP_UNALIGN 0x0301
#define TRAP_DTB_FAULT 0x0381
#define TRAP_ITB_MISS 0x0181 /* I-tb miss */
#define TRAP_ITB_ACV 0x0081
#define TRAP_OPDEC 0x0481
#define TRAP_FEN 0x0581
#define TRAP_PAL 0x2001
/* added for compat with ev5 simulator */
#define TRAP_DTB_ACV TRAP_DTB_FAULT
#if 0
/* funky. Is it real? bugnion
*/
#define TRAP_ITB_DPE 0x0FE1
#define TRAP_ITB_TPE 0x0BE1
#endif
#define IO_LOC 39 /* bit position to select I/O space */
/* size of the TB's **********************************************************/
#define MAX_ITB (48)
#define MAX_SDTB (64)
#define MAX_DTB MAX_SDTB
#ifdef bogus
#define MAX_LDTB (1) /*Bogus*/
#endif
/* number of instructions executed following a branch ************************/
#define power_up_pc (1)
/* Memory Management Control Status Register Bits (MM_CSR) *******************/
/**$$HA**/
#define MM_WR 0
#define MM_ACV 1
#define MM_FOR 2
#define MM_FOW 3
#define MM_DMISS 4
#define MM_BVA 5
#define MM_RA 6
/*#define MM_PALS 11 */
#define MM_OPC 11
/*****************************************************************************/
/* define the IPR's */
/*****************************************************************************/
#define MAX_IPR (4096*2) /* 12bit valid index for IPR's */
#define MAX_ADU_IPR (128)
/*EV5*/
#define IPR_PMCTR (0x11C)
#define IPR_ISR (0x100)
#define IPR_INTID (0x111)
#define IPR_ASTSR (0x109) /* ASTRR in manual (bugnion) */
#define IPR_ASTER (0x10A)
#define IPR_SIRR (0x108)
/***#define IPR_SICR (0x108) ***/
#define IPR_HWINT_CLR (0x115)
#define IPR_SL_XMIT (0x116)
#define IPR_SL_RCV (0x117)
#define IPR_ICERRSTAT (0x11A)
#define IPR_ICROWMAP (0x11B)
#define IPR_DCFILLERR (0x211)
#define IPR_DCERRSTAT (0x212)
#define IPR_DCTESTCTL (0x213)
#define IPR_DCTESTTAG (0x214)
#define IPR_DCTESTTAGT (0x215)
#define IPR_DCMODE (0x216)
#define IPR_MAFMODE (0x217)
#define IPR_MCSR (0x20F)
#define IPR_IC_FLUSH (0x119)
#define IPR_DC_FLUSH (0x210)
#define IPR_CC (0x20D)
#define IPR_CC_CTL (0x20E)
#define IPR_IPL (0x110) /* IPLR in manual */
#define IPR_PS (0x10F)
/* define IPR_ICM IPR_PS */
#define IPR_PAL_BASE (0x10E)
#define IPR_EXC_ADDR (0x10B)
#define IPR_EXC_SUM (0x10C)
#define IPR_EXC_MASK (0x10D)
#define IPR_MM_STAT (0x205)
#define IPR_ITB_TAG (0x101)
#define IPR_ITB_PTE (0x102)
#define IPR_ITB_ASN (0x103)
#define IPR_IPTE_TEMP (0x104)
#define IPR_IVA (MAX_IPR - 2) /* Be careful */ /* XXX bugnion NI */
#define IPR_IVA_F (0x112) /* XXX bugnion NI */
#define IPR_IVPTBR (0x113)
#define IPR_ICSR (0x118)
#define IPR_ALT_MODE (0x20C)
#define IPR_DTB_ASN (0x200)
#define IPR_DTB_CM (0x201)
#define IPR_DTB_TAG (0x202)
#define IPR_DTB_PTE (0x203)
#define IPR_DPTE_TEMP (0x204)
#define IPR_VA (0x206)
#define IPR_VA_F (0x207)
#define IPR_VA_FORM IPR_VA_F
#define IPR_MVPTBR (0x208)
#define IPR_DTBIA (0x20A)
#define IPR_DTBIAP (0x209)
#define IPR_DTBIS (0x20B)
#define IPR_ITBIA (0x105)
#define IPR_ITBIAP (0x106)
#define IPR_ITBIS (0x107)
/*REST*/
#define EVX$IPR_IBOX (1<<5)
#define EVX$IPR_ABOX (1<<6)
#define EVX$IPR_DTB_CTL (0x0)
#define EVX$IPR_MM_CSR (EVX$IPR_ABOX | 4)
#define EVX$IPR_BIU_ADDR (EVX$IPR_ABOX | 9)
#define EVX$IPR_BIU_STAT (EVX$IPR_ABOX | 10)
#define EVX$IPR_DC_ADDR (EVX$IPR_ABOX | 11)
#define EVX$IPR_DC_STAT (EVX$IPR_ABOX | 12)
#define EVX$IPR_FILL_ADDR (EVX$IPR_ABOX | 13)
#define EVX$IPR_ABOX_CTL (EVX$IPR_ABOX | 14)
#define EVX$IPR_BIU_CTL (EVX$IPR_ABOX | 18)
#define EVX$IPR_FILL_SYNDROME (EVX$IPR_ABOX | 19)
#define EVX$IPR_BC_TAG (EVX$IPR_ABOX | 20)
#define EVX$IPR_INTR_FLAG (EVX$IPR_ABOX | 22)
#define EVX$IPR_LOCK_FLAG (EVX$IPR_ABOX | 23)
#define EVX$IPR_HIRR (EVX$IPR_IBOX | 12)
#define EVX$IPR_ASTRR (EVX$IPR_IBOX | 14)
#define EVX$IPR_HIER (EVX$IPR_IBOX | 16)
#define EVX$IPR_SIER (EVX$IPR_IBOX | 17)
#define EVX$IPR_SL_CLR (EVX$IPR_IBOX | 19)
#define EVX$IPR_ISSUE_CHK (EVX$IPR_IBOX | 29)
#define EVX$IPR_SINGLE_ISSUE (EVX$IPR_IBOX | 30)
#define EVX$IPR_DUAL_ISSUE (EVX$IPR_IBOX | 31)
/**PAL temps */
#define IPR_PAL (0x140)
#define IPR_PAL_R0 (IPR_PAL | 0)
#define IPR_PAL_R1 (IPR_PAL | 1)
#define IPR_PAL_R2 (IPR_PAL | 2)
#define IPR_PAL_R3 (IPR_PAL | 3)
#define IPR_PAL_IMPURE (IPR_PAL_R3)
#define IPR_PAL_R4 (IPR_PAL | 4)
#define IPR_PAL_R5 (IPR_PAL | 5)
#define IPR_PAL_R6 (IPR_PAL | 6)
#define IPR_PAL_R7 (IPR_PAL | 7)
#define IPR_PAL_R8 (IPR_PAL | 8)
#define IPR_PAL_R9 (IPR_PAL | 9)
#define IPR_PAL_R10 (IPR_PAL | 10)
#define IPR_PAL_R11 (IPR_PAL | 11)
#define IPR_PAL_R12 (IPR_PAL | 12)
#define IPR_PAL_R13 (IPR_PAL | 13)
#define IPR_PAL_R14 (IPR_PAL | 14)
#define IPR_PAL_R15 (IPR_PAL | 15)
#define IPR_PAL_R16 (IPR_PAL | 16)
#define IPR_PAL_WHAMI (IPR_PAL_R16)
#define IPR_PAL_R17 (IPR_PAL | 17)
#define IPR_PAL_R18 (IPR_PAL | 18)
#define IPR_PAL_R19 (IPR_PAL | 19)
#define IPR_PAL_R20 (IPR_PAL | 20)
#define IPR_PAL_R21 (IPR_PAL | 21)
#define IPR_PAL_R22 (IPR_PAL | 22)
#define IPR_PAL_R23 (IPR_PAL | 23)
#define IPR_PAL_R24 (IPR_PAL | 24)
#define IPR_PAL_R25 (IPR_PAL | 25)
#define IPR_PAL_R26 (IPR_PAL | 26)
#define IPR_PAL_R27 (IPR_PAL | 27)
#define IPR_PAL_R28 (IPR_PAL | 28)
#define IPR_PAL_R29 (IPR_PAL | 29)
#define IPR_PAL_R30 (IPR_PAL | 30)
#define IPR_PAL_R31 (IPR_PAL | 31)
#define EVX$IPR_FP_CTL (MAX_IPR -1)
/*****************************************************************************/
/* define the Implementation specific code */
/*****************************************************************************/
#undef EVX$OPC_HW_MTPR
#undef EVX$OPC_HW_MFPR
#undef EVX$OPC_HW_LD
#undef EVX$OPC_HW_ST
#undef EVX$OPC_HW_REI
#define EVX$OPC_HW_MTPR (0x1D)
#define EVX$OPC_HW_MFPR (0x19)
#define EVX$OPC_HW_LD (0x1B)
#define EVX$OPC_HW_ST (0x1F)
#define EVX$OPC_HW_REI (0x1E)
/* this is where I start (bugnion) */
#include "addr_layout.h"
typedef union ev5_hwldst_format {
struct {
signed disp:10;
unsigned lock_cond:1; /* lock or cond */
unsigned vpte:1; /* load only */
unsigned quad:1;
unsigned wrtck:1; /* load only */
unsigned alt:1;
unsigned phys:1;
unsigned rb:5;
unsigned ra:5;
unsigned opcode:6;
} hwmem_format;
uint32 word;
} ev5_hwldst_format;
/* PAL MODE & shadow registers */
#define ISP_USE_SHADOW_REGISTERS(_v) (((_v)>>30)&1)
#define CURRENT_MODE(_p) ((_p)->ipr[IPR_PS] & (3<<3))
#define KERNEL_MODE (0<<3)
#define SUPERVISOR_MODE (1<<3)
#define USER_MODE (3<<3)
#define FPENABLED(_p) ((_p)->ipr[IPR_ICSR]>>26&1)
/* *************************************************************************
* Processor state macros. All take the IPR register as a parameter
* **************************************************************************/
/* ITLB access */
#define ISP_ISP0ENABLED(_ipr) (_ipr[IPR_ICSR]>>28&1)
#define ISP_ISP1ENABLED(_ipr) (_ipr[IPR_ICSR]>>29&1)
#define ISP_SP0EXECUTE(_ipr) ((_ipr[IPR_PS]>>3&3)==0)
#define ISP_SP1EXECUTE(_ipr) ISP_SP0EXECUTE(_ipr)
#define ISP_ITLBPROT(_ipr) (1<<(_ipr[IPR_PS]>>3))
/* DTLB access */
#define ISP_DSP0ENABLED(_ipr) (_ipr[IPR_MCSR]>>1&1)
#define ISP_DSP1ENABLED(_ipr) (_ipr[IPR_MCSR]>>2&1)
#define ISP_SP0ACCESS(_ipr) ((_ipr[IPR_DTB_CM]>>3&3)==0)
#define ISP_SP1ACCESS(_ipr) ISP_SP0ACCESS(_ipr)
#define ISP_DTLBPROT(_ipr) (1<<(_ipr[IPR_DTB_CM]>>3))
#define ISP_SP0ACCESS_ALT(_ipr) ((_ipr[IPR_ALT_MODE]>>3&3)==0)
#define ISP_SP1ACCESS_ALT(_ipr) ISP_SP0ACCESS_ALT(_ipr)
#define ISP_DTLBPROT_ALT(_ipr) (1<<(_ipr[IPR_ALT_MODE]>>3))
/* ASN */
#define ISP_CURRENT_IASN(_ipr) (_ipr[IPR_ITB_ASN]>>4)
#define ISP_CURRENT_DASN(_ipr) (_ipr[IPR_DTB_ASN]>>57)
#endif