/*
 * Copyright (C) 1996-1998 by the Board of Trustees
 *    of Leland Stanford Junior University.
 * 
 * This file is part of the SimOS distribution. 
 * See LICENSE file for terms of the license. 
 *
 */

/****************************************************************
 * cache.c
 * 
 * $Author: blythe $
 * $Date: 2002/05/29 01:09:10 $
 *****************************************************************/
#include <bstring.h>
#include <sys/types.h>
#include <sys/mman.h>
#include <unistd.h>
#include <stdlib.h>

#include "annotations.h"
#include "embra.h"
#include "cache.h"
#include "directory.h"
#include "decoder.h"
#include "mem_control.h"
#include "driver.h"
#include "main_run.h"
#include "qc.h"
#include "translator.h"
#include "clock.h"
#include "callout.h"
#include "stats.h"
#include "hw_events.h"
#include "simutil.h"
#include "addr_layout.h"
#ifdef MEM_ANNOTATIONS
#include "annotations.h"
#include "clock.h"
#endif
#include "addr_layout.h"

#define NOT_LAST_IN_SLINE(_Addr) (((uint)(_Addr)+INST_SIZE) & (SCACHE_LINE_SIZE - 1 ))
#define SCACHE_TAG_BASE_ADDR(_cpu) ((PLN*) \
(CACHE_TAG_START + ((_cpu) * CACHE_TAG_SIZE) ) )
  /* Replacement Hints are no longer implemented, but with
     Directory_Elimitate they could be  */
/* NOTE: these can not be used in parallel cache simulation */

/*--------------------------------------*/
/* cache & qc_p/Physarray debug support */

/* log all cache misses */
/* #define LOG_MISS_ALL */

/* log all misses on cacheline xxx, stop at PC, CC=EMP.cycleCount*/
/* #define LOG_MISS 
   #define STOP_PC 0x60007078
   #define STOP_CC 305448
   */

/* count misses for every cacheline */
/* #define DEBUG_PA */

/* insert cache consistency checks */
/* #define DEBUG_CACHE */

/*--------------------------------------*/
static void Cache_CommitRef(int cpuNum, PA pAddr, VA vAddr, PA pcPAddr,
                            EmVQCMemState state, int flags);
void cache_consistency_check( int cpuNum );

/* Data Structures */

static SimTime cachePrevInstrCount[SIM_MAXCPUS];

#ifdef gone_cleanup
static int lastMissState[SIM_MAXCPUS];
static int64 lastInstrCount[SIM_MAXCPUS];
#endif

static int64 iCount;

/* Miss handing table allocated in shared memory.  Only need 1 per CPU */
EmSMHT *emSMHT;

#ifdef DEBUG_PA
int *misscount;
#endif



void Cache_Init( int cpuNum )
{
   int i;

   if( embra.emode == EMBRA_PAGE ) {
	  return;
   }

   /* Clear the cache */
   if( embra.sequential ) {
      int cpu;
      for( cpu = 0; cpu<TOTAL_CPUS; cpu++) {
         /* To bootstrap the cache miss strategy MPinUP */
         emSMHT[cpu].state = MEM_I_SHARED;
         emSMHT[cpu].pAddr = INVALID_TAG;
         if (EMP[cpu].cache_tag ) continue;

         EMP[cpu].cache_tag = (PLN*) ZALLOC_PERM(CACHE_TAG_SIZE,"EmbraTags");

#ifdef DEBUG_PA
         misscount = (int *) ZALLOC_PERM((sizeof(int)*LINES_PER_CACHE),"EmbraTags");
#endif

         CPUPrint("0x%x D CACHE_TAG_BASE_%d 0x%x\n", 
                  EMP[cpu].cache_tag, cpu,
                  (uint)EMP[cpu].cache_tag + CACHE_TAG_SIZE );
         for( i = 0; i < LINES_PER_CACHE; i++ ) {
            EMP[cpu].cache_tag[i] = INVALID_TAG;

#ifdef DEBUG_PA
	    misscount[i]=0;
#endif

         }
      }
   } else { 
      ASSERT (0);
   }
}

/* Called when another processor steals a line  */
/* or called by EmbraDMAInval on a DMA transfer */
/* Pass the directory entry, so we only clobber possible conflicts */
/* Invalidate cache then pQC, then vQC because we have the directory
   lock & therefore avoid race conditions */
void Cache_Clobber( int machine, int cpuNum, PA pAddr, Dir_Entry cpu_bits, 
                    EmVQCMemState state )
{
   uint type = E_L2; 
   int i;
 
   if (!VQC_EXCL(state) ) {
      type |= E_DOWNGRADE;
   }
   ASSERT (!(cpu_bits>>cpuNum & 0x1));
   for(i = FIRST_CPU(machine); i <= LAST_CPU(machine); i++ ) { 
      /* 
       * No transition on invalidating CPU and on downgrades!
       */
      if (i!=cpuNum && !(type&E_DOWNGRADE)) { 
         if (CACHE_PLINE( EMP[i].cache_tag[SCACHE_INDEXOF(pAddr)] ) ==
             ADDR2SLINE( pAddr )) {  /* pAddr is in cache */
            ASSERT ((cpu_bits>>i) & 0x1);
            if (CACHE_SHARED(EMP[i].cache_tag[SCACHE_INDEXOF(pAddr)])) {
               L2_LINE_TRANS_EVENT(i, pAddr,type | E_EXTERNAL | E_FLUSH_CLEAN,0,
				   0,IS_KUSEG(EMP[i].PC));
            } else { 
               L2_LINE_TRANS_EVENT(i, pAddr,type | E_EXTERNAL | E_WRITEBACK,0,
				   0,IS_KUSEG(EMP[i].PC));
            }
        } else { 
#if should_work_does_not 
            ASSERT (!((cpu_bits>>i)&0x1));
#endif
            L2_LINE_TRANS_EVENT(i, pAddr,type | E_FAKE_EXTERNAL,0,0,
                                IS_KUSEG(EMP[i].PC));
         }
      }
      if( (cpu_bits>>i) & 0x1 ) {  
         if ( CACHE_PLINE( EMP[i].cache_tag[SCACHE_INDEXOF(pAddr)] ) ==
              ADDR2SLINE( pAddr ) ){  /* pAddr is in cache */
          
            if( VQC_EXCL(state) ) { 
               EMP[i].cache_tag[SCACHE_INDEXOF(pAddr)] = INVALID_TAG;
               /* If the intervener is getting exclusive control, then
                  fail the subsequent sc */
               if( ADDR2SLINE(EMP[i].LLAddr) == 
                   ADDR2SLINE(PHYS_TO_MEMADDR(M_FROM_CPU(i), pAddr)) )
                  EMP[i].LLAddr = 0;
               {
                  PA pPCAddr;
                  uint pc = EMP[i].PC;
                  pc = IN_BD(pc)?CLEAR_BD(pc)+INST_SIZE:pc;
                  pPCAddr = K0_TO_PHYS( non_excepting_tv(i,pc) );
                  if( ADDR2SLINE(pPCAddr) == ADDR2SLINE(pAddr) ) {
                     /* Ballsy */
                     EMP[i].jumpPC = (uint) continue_run_without_chaining;
                  }
               }
            } else {
               /* Downgrade doesn't invalidate chance of SC suceeding */
               /* RG: external line transition to shared. Is downgrade
                  ok if its state is already shared? I'll double check
                  just to make sure */
               

               EMP[i].cache_tag[SCACHE_INDEXOF(pAddr)] =
                  CACHE_SET_SHARED(CACHE_PLINE(EMP[i].cache_tag[SCACHE_INDEXOF(pAddr)]));
            }
            qc_clobber( pAddr, i, state );
         }
      }
   } 
}



/* This is called on a QC miss.  It drives all cache state transitions */

void UPCache_Ref( int cpuNum,
                  PA pAddr, 
                  VA vAddr, 
                  EmVQCMemState state )
{
   uint line_no           = SCACHE_INDEXOF( pAddr );
   uint pline             = ADDR2SLINE(pAddr);
   K0A  pcK0Addr          = non_excepting_tv(cpuNum, CLEAR_BD(EMP[cpuNum].PC));
   PA   pcPAddr;
   int pcConflict         = 0;
   int miss_handling_time = 0;
   uint type = E_L2;

   if (VQC_SHARED(state)) {
      type |= E_READ;
   } else {
      type |= E_WRITE;
   }
   ASSERT( NUM_CPUS(M_FROM_CPU(cpuNum)) == 1 );
   /* Otherwise our PC is not mapped! */
   ASSUME( pcK0Addr );
   if( pcK0Addr ) {
      /* We have to take action on a conflict if our PC is mapped data
         reference and our PC map to the same line */
      pcPAddr    = K0_TO_PHYS_REMAP( pcK0Addr, cpuNum );
      pcConflict = ( !VQC_INST(state) ) &&
         (line_no == SCACHE_INDEXOF( pcPAddr ) );
   }

#ifdef DEBUG_CACHE
   static int miss_count;

   miss_count++;
   if( miss_count > 100000 && (miss_count % 10000) == 0 ) {
      cache_consistency_check( cpuNum );
   }
#endif


   /*******************/

#ifdef COMMENTOUT
   CPUPrint("Cache Entry PC 0x%x st 0x%x vAddr 0x%x pAddr 0x%x pline 0x%x ln %d ctag 0x%x\n",
            EMP[cpuNum].PC,
            state,
            vAddr,
            pAddr,
            pline,
            line_no
            EMP[cpuNum].cache_tag[line_no] );
#endif

   if( pline == CACHE_PLINE( EMP[cpuNum].cache_tag[line_no] ) && 
       CACHE_VALID( EMP[cpuNum].cache_tag[line_no] ) ) {
      /* If permissions match, then its a cache hit, and vQC miss */
      /* By above test cache_tag is valid, so only need to check excl */
      VASSERT( !VQC_SHARED( state ) || 
               CACHE_VALID( EMP[cpuNum].cache_tag[line_no] ),
               ("State 0x%x, line_no %d pline 0x%x\n", 
                state, line_no, pline) );
      if( VQC_SHARED( state ) ||
          ( VQC_EXCL( state) && 
            CACHE_EXCL( EMP[cpuNum].cache_tag[line_no] ) ) ) {
         /* real cache hit, vQC miss */
         set_qc_state( cpuNum, ADDR2SLINE(vAddr), pline, state );
         return;
      } else {
         /* Upgrade--Free on a uniprocessor */
         /* RG upgrading from shared to exclusive. For a UP,
            this is simply a transition.... */
         CACHE_SINC( cpuNum, CURRENT_MODE(EMP), upgrades );
         miss_handling_time += 0;

#ifdef  LOG_MISS

         if (line_no == LOG_MISS){
            CPUPrint("Cache MISS-upgrade on %d , PC = %x, cycleCount = %lld\n",LOG_MISS,EMP[cpuNum].PC,EMP[cpuNum].cycleCount);
         }

#endif

         goto accountingDone;
      }
   }

   miss_handling_time += MEM_CYCLE_TIME;
   ASSERT (MEM_CYCLE_TIME);

   CACHE_INC( cpuNum, CURRENT_MODE(&EMP[cpuNum]), i_miss, d_miss, state );
#ifdef  LOG_MISS

   if (line_no == LOG_MISS)
      CPUPrint("Cache MISS on %d , PC = %x, cycleCount = %lld\n",LOG_MISS,EMP[cpuNum].PC,EMP[cpuNum].cycleCount);
   if ((EMP[cpuNum].PC==STOP_PC)&&(EmbraCpuCycleCount(cpuNum)==STOP_CC))
       ASSERT(0);

#endif
   
   { 
#ifdef DEBUG_PA
      misscount[line_no]++;
#endif

#ifdef LOG_MISS_ALL

      CPUPrint("Cache MISS on %x , PC = %x, cycleCount = %lld\n",line_no,EMP[cpuNum].PC,EmbraCpuCycleCount(cpuNum));
      if ((EMP[cpuNum].PC==STOP_PC)&&(EmbraCpuCycleCount(cpuNum)==STOP_CC))
          ASSERT(0);

#endif

      /* RG Record the miss after the transition */
      if( CACHE_VALID( EMP[cpuNum].cache_tag[line_no] ) ) {
         /* RG: The current entry is booted, regardless of if it's
            correct or not. */
         uint type = E_L2;
         uint oldAddr;
         
         if (CACHE_EXCL( EMP[cpuNum].cache_tag[line_no])) {
            type |= E_WRITEBACK;
         } else {
            type |= E_FLUSH_CLEAN;
         }
         
         /* Kick out previous line. Need to do a transition here */
         oldAddr = SLINE2ADDR(CACHE_PLINE(EMP[cpuNum].cache_tag[line_no]));
         L2_LINE_TRANS_EVENT(cpuNum,oldAddr,type, vAddr, 0,
                             IS_KUSEG(EMP[cpuNum].PC));
      }  
      
      if (VQC_INST(state)) {
         L2_IMISS_EVENT( EmbraCpuCycleCount(cpuNum),
                         cpuNum, vAddr, pAddr, miss_handling_time,
                         type | E_I); 
      } else {
         VA pc = CLEAR_BD(EMP[cpuNum].PC);
      
         L2_DMISS_EVENT( EmbraCpuCycleCount(cpuNum),
                         cpuNum, pc, vAddr, pAddr, miss_handling_time,
                         type | E_D, 0);
      }
   }

accountingDone:

   /* If there is a previous entry in this line, kick it out */
   if( CACHE_VALID( EMP[cpuNum].cache_tag[line_no] ) ) {

      /* This could be an upgrade which means we are kicking out the
         shared entry, but that is just redundant work, not incorrect */
      if (embra.useVQC){
         set_qc_state( 
                      cpuNum,
                      PQC_VLINE(
                                EMP[cpuNum].qc_p[
                                            CACHE_PLINE(
                                                        EMP[cpuNum].cache_tag[line_no])]),
                      CACHE_PLINE( EMP[cpuNum].cache_tag[line_no] ), 
                      MEM_INVALID );
      } else { /* !embra.useVQC */
         set_qc_state( 
                      cpuNum,0,
                      CACHE_PLINE( EMP[cpuNum].cache_tag[line_no] ), 
                      MEM_INVALID );

      }


   }

   /* Set the qc entry and the cache tags. */
   /* If we had a conflict then set the qc and tags to the I entry  */
   /* XXX - This means that UP MUST return the */
   /* address so the QC does not rewind (that will infinite loop) */
   if( pcConflict && 
       !IN_BD( EMP[cpuNum].PC )  &&
       NOT_LAST_IN_SLINE( EMP[cpuNum].PC ) ) {
      /* We have detected a conflict. Between the PC and the miss address. */
      /* What should happen here is 
         1. PC line is present in cache
         2. l/s is executed, cache miss and PC line evicted
         3. l/s completes even though PC line is not in cache
         4. If l/s in delay slot then l/s owns line, else 
         Imiss, and PC owns line
         However, we don't emit an icache check after every l/s for
         performance. Therefore, just count the I miss, and assign the
         qc to the proper party
         */

      /* Data miss was charged earlier, charge I miss */

      /* Going with what emmett says--charge I miss now.
         Use original miss_handling time--don't charge twice. */

      /* Transition to evict vaddr (data),
         IMiss needs to bring in next pc +4.. */

      if ( VQC_EXCL(state)) {
         type = E_L2 | E_WRITEBACK;
      } else {
         type = E_L2 | E_FLUSH_CLEAN;
      }

      L2_LINE_TRANS_EVENT(cpuNum, pAddr, type, EMP[cpuNum].PC, 0,
                          IS_KUSEG(EMP[cpuNum].PC));
      L2_IMISS_EVENT( EmbraCpuCycleCount(cpuNum) + miss_handling_time,
                      cpuNum, EMP[cpuNum].PC, pcPAddr, miss_handling_time,
                      type | E_I); 


      miss_handling_time += MEM_CYCLE_TIME;

      CACHE_INC( cpuNum, CURRENT_MODE(&EMP[cpuNum]), i_miss, d_miss, MEM_I_SHARED );
   
      /* Set the data QC to inaccessible */
      set_qc_state( cpuNum, ADDR2SLINE(vAddr), pline, MEM_INVALID );

      /* No need to CLEAR_BD */
      /* Set the instr QC to accessible */
      set_qc_state( cpuNum, ADDR2SLINE(CLEAR_BD(EMP[cpuNum].PC)), 
                    ADDR2SLINE(pcPAddr), 
                    MEM_I_SHARED );
      EMP[cpuNum].cache_tag[line_no] = CACHE_SET_SHARED( ADDR2SLINE(pcPAddr) );
   } else {
      /* Set the new line's quick check to the proper, accesible state */
      /* Note that this invalidates phys_info[pline].virt_line */
      /* Since the new entry could be the same as the old ( like on an */
      /* upgrade the invalidate happens first */
      set_qc_state( cpuNum, ADDR2SLINE(vAddr), pline, state );
      /* Update Mshade tags */
      if( VQC_SHARED( state ) ) {
         EMP[cpuNum].cache_tag[line_no] = CACHE_SET_SHARED( pline );
         /* RG here are the transitions... */
      } else {
         ASSERT( VQC_EXCL( state ) );
         EMP[cpuNum].cache_tag[line_no] = CACHE_SET_EXCL( pline );
         /* RG here are the transitions... */
      }
   }
   EMP[cpuNum].cycleCountdown -= miss_handling_time;
   CACHE_INC_BY(cpuNum, CURRENT_MODE(&EMP[cpuNum]), 
                i_stall_cyc, d_stall_cyc, state,
                miss_handling_time );
}



void MPinUPCache_Ref( int cpuNum, 
                      PA pAddr, 
                      VA vAddr, 
                      EmVQCMemState state )
{
   uint pline             = ADDR2SLINE(pAddr);
   uint line_no           = SCACHE_INDEXOF(pAddr);
   int smht_flags         = 0;
   int miss_handling_time = 0;
   MA  maPCAddr           = 0;

   
  if (interest(pAddr)) {
      LogEntry("ref",cpuNum,"pAddr=%08x state=%x msstate=%d \n",pAddr,state,
               MSCacheState(cpuNum,pAddr));
   }
   /* no sc in delay slot */
   if( !IN_BD( EMP[cpuNum].PC ) ){
      maPCAddr =
         K0_TO_MEMADDR(M_FROM_CPU(cpuNum),
                       non_excepting_tv(cpuNum,EMP[cpuNum].PC));
      ASSERT(maPCAddr);
      if( MAJOR_OPCODE(*(uint*)maPCAddr) == sc_op ) {
         smht_flags |= SMHT_SC;
      }
   } else {
      smht_flags |= SMHT_BD;
   }

   if( pline == CACHE_PLINE( EMP[cpuNum].cache_tag[line_no] ) && 
       CACHE_VALID( EMP[cpuNum].cache_tag[line_no] ) ) {
      /* If permissions match, then this is a real cache hit, and a qc */
      /* miss */ 
      /* By above test cache_tag is valid, so only need to check excl */
      /* VASSERT( !VQC_SHARED( state ) || 
               CACHE_VALID( EMP[cpuNum].cache_tag[line_no] ),
               ("State %d, line_no %d\n", state, line_no) ); */
      if( VQC_SHARED( state ) ||
          ( VQC_EXCL( state) && 
            CACHE_EXCL( EMP[cpuNum].cache_tag[line_no] ) ) ) {
         /* Cache hit */
         /* Update qc to present access status.  I could do this based
            on the cache tag value, but why bother? */
         set_qc_state( cpuNum, ADDR2SLINE(vAddr), pline, state );
         if (interest(pAddr)) {
            LogEntry("ref_qc",cpuNum,"pAddr=%08x state=%x msstate=%d\n",pAddr,state,
                     MSCacheState(cpuNum,pAddr));
         }       
         return;
      } else {
         /* Upgrade */
         smht_flags |= SMHT_UPGRADE;
         if (interest(pAddr)) {
            LogEntry("ref_upg",cpuNum,"pAddr=%08x state=%x msstate=%d\n",pAddr,state,
                     MSCacheState(cpuNum,pAddr));
         }
         /* Remove xfer time */
         miss_handling_time += UPGRADE_TIME;
         goto accountingDone;
      }
   }
   miss_handling_time += MEM_CYCLE_TIME;
accountingDone:

#ifdef notdef
   CPUPrint("R %d %-4lld 0x%-8x VA 0x%-8x PA 0x%-8x 0x%-2x\n",
          cpuNum,
          EmbraCpuInstrCount(cpuNum),
          EMP[cpuNum].PC,
          vAddr,pAddr, state);
#endif

   iCount = EmbraCpuInstrCount(cpuNum);
   ASSERT( iCount >= cachePrevInstrCount[cpuNum]);

   cachePrevInstrCount[cpuNum] = iCount;


/* 
 * XXX Emmett has this commented out, but told me to execute it. (ed)
 */
/* do we need this ? */

#ifdef notdef  

   if( !iCount ) {
      /* Update vQC and cache tags */
      Cache_CommitRef( cpuNum, pAddr, vAddr, 0, state, smht_flags);
      if( interest(pAddr)) { 
         LogEntry("cc_ref_0",cpuNum,"pAddr=%08x state=%x msstate=%d\n",pAddr,state,
                  MSCacheState(cpuNum,pAddr));
      }
   }
#endif
   if( emSMHT[cpuNum].iCount == iCount ) {
      /* Commit the previous reference */
#ifdef notdef  
      CPUPut("EMBRA SMHT %d %-4lld 0x%-8x VA 0x%-8x PA 0x%-8x 0x%-2x 0x%-8x PA 0x%-8x 0x%-2x\n",
             cpuNum,
             emSMHT[cpuNum].iCount,
             EMP[cpuNum].PC,
             emSMHT[cpuNum].vAddr,
             emSMHT[cpuNum].pAddr,
             emSMHT[cpuNum].state,
             vAddr,
             pAddr,
             state);
#endif

      if( !( VQC_INST( emSMHT[cpuNum].state ) &&
             VQC_DATA(state)) ) {
         /* ASSERT(!iCount || state == emSMHT[cpuNum].state);*/
         if (emSMHT[cpuNum].pAddr != INVALID_TAG) { 
            Cache_CommitRef(cpuNum, 
                            emSMHT[cpuNum].pAddr, 
                            emSMHT[cpuNum].vAddr, 
                            emSMHT[cpuNum].pcPAddr,
                            (EmVQCMemState)emSMHT[cpuNum].state,
                            emSMHT[cpuNum].smht_flags);
            
            /*
             * We used the MHT, now get rid of it (ed) 
             */
            if (interest(emSMHT[cpuNum].pAddr)) { 
               LogEntry("cc_ref_1",cpuNum,"pAddr=%08x state=%x msstate=%d\n",pAddr,state,
                        MSCacheState(cpuNum,emSMHT[cpuNum].pAddr));    
            } 
            emSMHT[cpuNum].pAddr = INVALID_TAG;
         }
         if( VQC_DATA(state) ) {
            if( !(smht_flags & SMHT_BD) ){
               if( NOT_LAST_IN_SLINE(EMP[cpuNum].PC) ){
                  /* not in bd and NLISL means not last on page */
                  PA pPCAddr = MEMADDR_TO_PHYS(M_FROM_CPU(cpuNum),
                                               maPCAddr) + INST_SIZE; 
                  uint tag = EMP[cpuNum].cache_tag[SCACHE_INDEXOF(pPCAddr)];
                  /* if( line_no == SCACHE_INDEXOF(MEMADDR_TO_PHYS(maPCAddr)) ){ */ 
                  if( !CACHE_VALID(tag) ||
                      CACHE_PLINE(tag) != ADDR2SLINE(pPCAddr) ) {
                     
                     EMP[cpuNum].cycleCountdown -= MEM_CYCLE_TIME; 
                     smht_flags = 0; 
                     if( MAJOR_OPCODE(*(uint*)(maPCAddr + INST_SIZE)) == sc_op ) 
                        smht_flags = SMHT_SC; 
                     Cache_CommitRef( cpuNum,
                                      pPCAddr,
                                      /* dref completed and we are not in bd */
                                      EMP[cpuNum].PC + INST_SIZE,
                                      0,
                                      MEM_I_SHARED,
                                      smht_flags);
                     emSMHT[cpuNum].iCount++;
                     emSMHT[cpuNum].state = MEM_I_SHARED;
                     if (interest(EMP[cpuNum].PC + INST_SIZE)) { 
                        LogEntry("cc_ref_2",cpuNum,"pAddr=%08x state=%x msstate=%d\n",
                                 EMP[cpuNum].PC + INST_SIZE ,state,
                                 MSCacheState(cpuNum,EMP[cpuNum].PC + INST_SIZE));     
                     }
                  }
               }
            }
         }
         if (interest(pAddr)) {
            LogEntry("refret",cpuNum,"pAddr=%08x state=%x msstate=%d\n",pAddr,state,
                     MSCacheState(cpuNum,pAddr));
         }
         return;
      }
   }
   EMP[cpuNum].cycleCountdown -= miss_handling_time;

   if( (EMP[cpuNum].blockCycleCountdown - miss_handling_time) <= 0 ) {
      if( !(smht_flags & SMHT_BD) ) {
         emSMHT[cpuNum].pAddr   = pAddr;
         emSMHT[cpuNum].vAddr   = vAddr;
         emSMHT[cpuNum].pcPAddr = 0;
         emSMHT[cpuNum].state   = state;
         emSMHT[cpuNum].smht_flags   = smht_flags;
         emSMHT[cpuNum].iCount  = iCount;
         EMP[cpuNum].jumpPC = (uint)continue_run_without_chaining;
         if (interest(pAddr)) {
            LogEntry("ref_tc",cpuNum,"pAddr=%08x state=%x msstate=%d\n",pAddr,state,
                     MSCacheState(cpuNum,pAddr));
         }     
         ReenterTC_CX(&EMP[cpuNum]);
         /* NOT REACHED */
      }
   }
   /* Update vQC and cache tags */
   Cache_CommitRef( cpuNum, pAddr, vAddr, 0, state, smht_flags);
   emSMHT[cpuNum].iCount = iCount;
   if (interest(pAddr)) {
      LogEntry("refend",cpuNum,"pAddr=%08x state=%x msstate=%d \n",pAddr,state,
               MSCacheState(cpuNum,pAddr));
   }

}

#ifdef OLD_VERSION_EB
void MPinUPCache_Ref_old( int cpuNum, 
                      PA pAddr, 
                      VA vAddr, 
                      EmVQCMemState state )
{

   uint line_no           = SCACHE_INDEXOF( pAddr );
   uint pline             = ADDR2SLINE(pAddr);
   VA   vpc               = CLEAR_BD(EMP[cpuNum].PC);
   K0A  pcK0Addr          = non_excepting_tv(cpuNum, CLEAR_BD(EMP[cpuNum].PC));
   PA   pcPAddr;
   int smht_flags         = 0;
   int miss_handling_time = 0;
   int cx_me              = 0;

   
   /* Otherwise our PC is not mapped! */
   ASSUME( pcK0Addr );
   if( pcK0Addr ) {
      if( MAJOR_OPCODE( *(uint*)K0_TO_MEMADDR( M_FROM_CPU(cpuNum),
                                               pcK0Addr ) ) == sc_op ) {
         smht_flags |= SMHT_SC;
      }
      pcPAddr    = K0_TO_PHYS_REMAP( pcK0Addr, cpuNum );
      if( ( !VQC_INST(state) ) &&
          (line_no == SCACHE_INDEXOF( pcPAddr ) ) ) {
         /* PC and data ref map to same cache line */
         smht_flags |= SMHT_PCCONFLICT;
      }
   }

   if( pline == CACHE_PLINE( EMP[cpuNum].cache_tag[line_no] ) && 
       CACHE_VALID( EMP[cpuNum].cache_tag[line_no] ) ) {
      /* If permissions match, then this is a real cache hit, and a qc */
      /* miss */ 
      /* By above test cache_tag is valid, so only need to check excl */
      /* VASSERT( !VQC_SHARED( state ) || 
               CACHE_VALID( EMP[cpuNum].cache_tag[line_no] ),
               ("State %d, line_no %d\n", state, line_no) ); */
      if( VQC_SHARED( state ) ||
          ( VQC_EXCL( state) && 
            CACHE_EXCL( EMP[cpuNum].cache_tag[line_no] ) ) ) {
         /* Cache hit */
         /* Update qc to present access status.  I could do this based
            on the cache tag value, but why bother? */
         set_qc_state( cpuNum, ADDR2SLINE(vAddr), pline, state );
         return;
      } else {
         /* Upgrade */
         smht_flags |= SMHT_UPGRADE;
         miss_handling_time += UPGRADE_TIME;
         goto accountingDone;
      }
   }
   miss_handling_time += MEM_CYCLE_TIME;
accountingDone:

   /* XXX - Lasciate ogni speranza
      If the cost of handling the miss, plus the rest of the
      instructions in the block is larger than the current quantum,
      then we should context switch and let more time pass.  There are
      a couple of exceptions
      1. Translator/pc_tc lookup can't deal with delay slot instructions
      2. Give priority to sc that can succeed, otherwise livelock
      3. Livelock can still occur.  Livelock is detected by multiple
      misses without the instruction count increasing.  There are two
      cases--an intra-cpu conflict or an inter-cpu conflict.
      Notes:
      cx  - processor context switch
      ret - return to emitted code, allowing reference to succeed,
            independent of vQC state
      I assume that processor timeQuantum < MemCycleTime
      XXX - I assume direct mapped cache
      a. Intra-cpu conflict--this is a pc/data conflict.
      Note: pc/data conflicts in the delay slot or on the last
      instruction of a cache line are not conflicts.
      Reality: data miss, then the instr miss on the next instruction
      (if that is in the same line as the data ref, and we are not in
      a delay slot).
      Simulator (format--action, cache simulator response):
      data miss
        cx
      instr miss (guaranteed b/c of cx) part I
        charge & set QC only if !BD(pc) && NOT_LAST_IN_SLINE(pc) & ret
      data miss part II
        no charge, don't set QC & ret
      Detection: part I  data then instr miss
                 part II instr then data miss
      Problem: If a line branches back to itself, we do not register
      the miss.  This is solved by having lines branch back to
      their icache check.
      b. Inter-cpu conflict--e.g. two cpus want the same line, at
      least one of them exclusively
      Reality: p1 data miss, p2's data miss, p1 succeeds/advances pc
      Simulator:
      p1 i|d shared miss
        cx
      p2 data excl miss
        cx
      p1 (i|d) shared miss
        no charge, set QC, ret
      Detection: last_miss_state == this_miss_state
      Note, p1's first reference could be data, and its second could
      be instr (indicating both an intra and inter cpu conflict), in
      that case, intra-cpu processing is still correct
      4. Final wrinkle--Intra-cpu conflicts that are possibly
      successful sc instructions can't cx the processor 
      Reality: see 3a
      Simulator:
      data miss
        charge data, 
        if !BD(pc) && !NOT_LAST_IN_SLINE
          charge instr, set QC to instr
        ret
      */
   iCount = EmbraCpuInstrCount(cpuNum);
   if( lastInstrCount[cpuNum] != iCount ) {
      if( (EMP[cpuNum].blockCycleCountdown - miss_handling_time) < 0 &&
          !IN_BD(EMP[cpuNum].PC) ) {
          if( !(smht_flags & SMHT_SC) || EMP[cpuNum].LLAddr == 0){
             cx_me = 1;
          } else {
             if( smht_flags & SMHT_PCCONFLICT ) {
                /* ASSERT( !IN_BD(EMP[cpuNum].PC ); */
                if( NOT_LAST_IN_SLINE(EMP[cpuNum].PC) ){
                   /* This is to catch case 4 */
                   smht_flags |= SMHT_DOUBLECOUNT;
                   miss_handling_time += MEM_CYCLE_TIME;
                }
             }
          }
      }
   } else {
      if( lastMissState[cpuNum] == state ) {
         /* Inter-cpu conflict */
         miss_handling_time = 0;
      } else {
         if( VQC_DATA(lastMissState[cpuNum]) &&
             VQC_INST(state) ) {
            /* Intra-cpu conflict part I (possibly inter-cpu conflict) */
            uint pc = EMP[cpuNum].PC;
            if( IN_BD(pc) || !NOT_LAST_IN_SLINE(pc) ){
               /* Spurious callout--no ireference in reality */
               lastMissState[cpuNum] = MEM_INVALID;
               return;
            }
         } else {
            if( VQC_INST(lastMissState[cpuNum]) &&
                VQC_DATA(state) ) {
               /* Intra-cpu conflict part II */
               /* Spurious callout--no dreference in reality */
               lastMissState[cpuNum] = MEM_INVALID;
               return;
            }
         }
      }
   }
   /* If this is a real miss, count it and charge stall time */
   if( miss_handling_time ) {
      uint type = E_L2;
      
      if (VQC_SHARED(state)) {
         type |= E_READ;
      } else {
         type |= E_WRITE;
      }
      
      EMP[cpuNum].cycleCountdown -= miss_handling_time;
      if( smht_flags & SMHT_UPGRADE ) {
         CACHE_SINC( cpuNum, CURRENT_MODE(&EMP[cpuNum]), upgrades );
         type |= E_UPGRADE;
      } else {
         CACHE_INC( cpuNum, CURRENT_MODE(&EMP[cpuNum]), i_miss, d_miss, state );
      }
    
      if (VQC_INST(state)) {
         ASSERT( !(type&E_UPGRADE));
         L2_IMISS_EVENT( EmbraCpuCycleCount(cpuNum),
                         cpuNum, vAddr, pAddr, miss_handling_time,
                         type | E_I); 
      } else {
         VA pc = CLEAR_BD(EMP[cpuNum].PC);
         L2_DMISS_EVENT( EmbraCpuCycleCount(cpuNum),
                         cpuNum, pc, vAddr, pAddr, miss_handling_time,
                         type | E_D, 0);
      }
    /* Charge stall time accounting*/      
      CACHE_INC_BY(cpuNum, CURRENT_MODE(&EMP[cpuNum]), 
                   i_stall_cyc, d_stall_cyc, state, miss_handling_time);
   }
   /* Update vQC and cache tags */
   Cache_CommitRef( cpuNum, pAddr, vAddr, pcPAddr, state, smht_flags);
   
   if( cx_me ) {
      lastMissState[cpuNum] = state;
      lastInstrCount[cpuNum] = iCount;
      EMP[cpuNum].jumpPC = (uint)continue_run_without_chaining;
      ReenterTC_CX(&EMP[cpuNum]);
   }
   lastMissState[cpuNum] = MEM_INVALID;
}

#endif /* OLD VERSION_EB */


static void Cache_CommitRef(int cpuNum, PA pAddr, VA vAddr, PA pcPAddr,
                            EmVQCMemState state, int flags)
{
   uint line_no = SCACHE_INDEXOF( pAddr );
   PLN  pline   = ADDR2SLINE( pAddr );
/*   int mode     = CURRENT_MODE(&EMP[cpuNum]);
     Dir_Entry      new_dir_entry; */ /* not used XXX */
   int miss_handling_time = (flags&SMHT_UPGRADE ? 
                             UPGRADE_TIME : MEM_CYCLE_TIME );
   uint type = E_L2;


   if( flags & SMHT_UPGRADE ) {
      CACHE_SINC( cpuNum, CURRENT_MODE(&EMP[cpuNum]), upgrades );
      type |= E_UPGRADE;
   } else {
      CACHE_INC( cpuNum, CURRENT_MODE(&EMP[cpuNum]), i_miss, d_miss, state );
   }
   if (VQC_SHARED(state)) {
      type |= E_READ;
   } else {
      type |= E_WRITE;
   }
 

   /* Like Mipsy, before I consult the caches, if this sc will fail,
      then just let it fail & don't let it grab any line or directory
      entry */
   if( (flags & SMHT_SC) && EMP[cpuNum].LLAddr == 0 ) {
      if (interest(pAddr)) { 
         LogEntry("sc_failed",cpuNum,"pAddr=%08x flags=%x \n",pAddr,flags);
      }
      return;
   }

   /* make sure that if this is an upgrade, the line is in the cache
    * If not warning + make it a miss (ed)
    */
   
   if (flags &SMHT_UPGRADE) {
      PA line1  = CACHE_PLINE(EMP[cpuNum].cache_tag[line_no]);
      PA line2  = ADDR2SLINE(pAddr);
      if (line1!=line2 || !CACHE_VALID( EMP[cpuNum].cache_tag[line_no])) { 
         LogEntry("EMBRA",cpuNum,"WARNING  Upgrade not in cache pAddr=0x%08x\n",
                    pAddr,SLINE2ADDR(line1));
         flags &= ~SMHT_UPGRADE;
         type  &= ~E_UPGRADE;
      } 
   }
         

  /* If there is a previous entry in this line, which is not this
      line, kick it out */
   if( CACHE_VALID( EMP[cpuNum].cache_tag[line_no] ) ) {
      /* Kick out previous line */
      /* If this is an upgrade this could be redundant work */
      if (!(flags &  SMHT_UPGRADE)) {
         uint type = E_L2;
         PA oldAddr = SLINE2ADDR(CACHE_PLINE(EMP[cpuNum].cache_tag[line_no]));
         if (CACHE_EXCL( EMP[0].cache_tag[line_no])) {
            type |= E_WRITEBACK;
         } else {
            type |= E_FLUSH_CLEAN;
         }
         if (IS_KSEG0(pAddr) || IS_KSEG1(pAddr) || IS_KSEG2(pAddr)) {
            type |= E_KERN_REPLACED;
         } else { 
            type |= E_USER_REPLACED;
         }
         if (!oldAddr) { 
            LogEntry("Ed's cautious",cpuNum,"Transition on line 0\n");
         } 
         L2_LINE_TRANS_EVENT(cpuNum,oldAddr,type, vAddr, 0,
                                 IS_KUSEG(EMP[cpuNum].PC));
      }
      

      if (embra.useVQC){
         set_qc_state(cpuNum, PQC_VLINE(EMP[cpuNum].qc_p[CACHE_PLINE(EMP[cpuNum].cache_tag[line_no])]),
                         CACHE_PLINE( EMP[cpuNum].cache_tag[line_no] ), 
                         MEM_INVALID );
      } else { /* !embra.useVQC */

         set_qc_state( 
                         cpuNum,0,
                         CACHE_PLINE( EMP[cpuNum].cache_tag[line_no] ), 
                         MEM_INVALID );

      }

      /* If we are evicting something (who is not us) with an ll
         outstanding, smash the LL regsiter. */
      if( CACHE_PLINE( EMP[cpuNum].cache_tag[line_no] ) == 
          ADDR2SLINE(EMP[cpuNum].LLAddr) &&
          pline != CACHE_PLINE( EMP[cpuNum].cache_tag[line_no] )) {
         EMP[cpuNum].LLAddr = 0;
      }
   }

   /*
    * transitions for the insertion fot he line in the cache
    */
   if (VQC_INST(state)) {
      ASSERT( !(type&E_UPGRADE));
      L2_IMISS_EVENT( EmbraCpuCycleCount(cpuNum),
                      cpuNum, vAddr, pAddr, miss_handling_time,
                      type | E_I); 
   } else {
      VA pc = CLEAR_BD(EMP[cpuNum].PC);
      L2_DMISS_EVENT( EmbraCpuCycleCount(cpuNum),
                      cpuNum, pc, vAddr, pAddr, miss_handling_time,
                      type | E_D, 0);
   }


   /* Set the qc entry and the cache tags. */
   /* If we have an intra-cpu conflict then 
      1. PC line is present in cache
      2. l/s is executed, cache miss and PC line evicted
      3. l/s completes even though PC line is not in cache
      4. If l/s in delay slot then l/s owns line, else 
      Imiss, and PC owns line
      However, we don't emit an icache check after every l/s for
      performance. Therefore, just count the I miss, and assign the
      qc to the proper party
      */
   /* XXX - This means that UP MUST return the */
   /* address so the QC does not rewind (that will infinite loop) */
   if( flags & SMHT_DOUBLECOUNT ){
      /* Data miss registered earlier, this is the imiss after the
         current data reference instruction */
      CACHE_INC( cpuNum, mode, i_miss, d_miss, MEM_I_SHARED );

      /* Register our data access with the directory */
      Directory_NoLock_Modify(cpuNum, pAddr,vAddr, state);
      /* Now do the conflict that will occur after the instruction is
         executed */
      /* Set the data QC to inaccessible */
      set_qc_state( cpuNum, ADDR2SLINE(vAddr), pline, MEM_INVALID );

      /* Register our instruction access with the directory */
      Directory_NoLock_Modify(cpuNum, pcPAddr,CLEAR_BD(EMP[cpuNum].PC),
                              MEM_I_SHARED);
      /* Set the instr QC to accessible */
      set_qc_state( cpuNum, ADDR2SLINE(CLEAR_BD(EMP[cpuNum].PC)), 
                          ADDR2SLINE(pcPAddr), 
                          MEM_I_SHARED );
      EMP[cpuNum].cache_tag[line_no] = 
         CACHE_SET_SHARED( ADDR2SLINE(pcPAddr) );
   } else {
      /* Register our access with the directory */
      Directory_NoLock_Modify(cpuNum, pAddr,vAddr, state);

      /* Set the new line's quick check to the proper, accesible state */
      set_qc_state( cpuNum, ADDR2SLINE(vAddr), pline, state );
      /* Update Embra tags */
      if( VQC_SHARED( state ) ) {
         EMP[cpuNum].cache_tag[line_no] = CACHE_SET_SHARED( pline );
      } else {
         ASSERT( VQC_EXCL( state ) );
         EMP[cpuNum].cache_tag[line_no] = CACHE_SET_EXCL( pline );
      }
   }
}



/* Called via backdoor to insure that cache state is consistent */
void cache_consistency_check( int cpuNum )
{
 int i, j;
 /* User, k0, k2 */
 int virt_qc_lines[3];
 int virt_qc_lines_backmapped[3];
 int virt_qc_lines_in_cache[3];
 int phys_qc_lines = 0;
 int phys_qc_lines_in_cache = 0;
 int num_repeated_plines = 0;
 int invalid_cache_tags=0;
 extern void qc_consistency_check(void);
#define LINE_TO_INDEX(_line) ( ((_line)<(ADDR2SLINE(K0BASE)))?0:((_line)>=ADDR2SLINE(K2BASE))?2:1)

 qc_consistency_check();
 for( i = 0; i < 3; i++ ) {
    virt_qc_lines[i] = 0;
    virt_qc_lines_backmapped[i] = 0;
    virt_qc_lines_in_cache[i] = 0;
 }
 for( i = 0; i < ADDR2SLINE(0xffffffff); i++ ) {
    if( EMP[cpuNum].qc_v[i] != MEM_INVALID ) {
       PLN pline;
       K0A k0a = non_excepting_tv(cpuNum, SLINE2ADDR(i) );
       if( !k0a ) {
          /* A line can be in the cache and not be mapped, but if its */
          /* in the virt QC, it has to be both mapped and in the cache */
          CPUPut("Line 0x%x not mapped\n", i);
          continue;
       }
       pline = ADDR2SLINE(K0_TO_PHYS_REMAP(k0a, cpuNum));
       virt_qc_lines[LINE_TO_INDEX(i)]++;
       if( PQC_VLINE(EMP[cpuNum].qc_p[pline]) == i ) {
          virt_qc_lines_backmapped[LINE_TO_INDEX(i)]++;
       }
       for( j = 0; j < LINES_PER_CACHE; j++ ) {
          if ( CACHE_PLINE( EMP[cpuNum].cache_tag[j] ) == pline ) {
             virt_qc_lines_in_cache[LINE_TO_INDEX(i)]++;
             break;
          }
       }
    }
 }
 CPUPut("VIRT (lines/bkmap/cache) KU/%d/%d/%d  K0/%d/%d/%d  K2/%d/%d/%d\n",
        virt_qc_lines[0],
        virt_qc_lines_backmapped[0],
        virt_qc_lines_in_cache[0],
        virt_qc_lines[1],
        virt_qc_lines_backmapped[1],
        virt_qc_lines_in_cache[1],
        virt_qc_lines[2],
        virt_qc_lines_backmapped[2],
        virt_qc_lines_in_cache[2] );

 for( i = 0; i < ADDR2SLINE(MEM_SIZE(M_FROM_CPU(cpuNum))); i++ ) {
    if( PQC_VALID(EMP[cpuNum].qc_p[i]) ){
       phys_qc_lines++;
       for( j = 0; j < LINES_PER_CACHE; j++ ) {
          if ( CACHE_PLINE( EMP[cpuNum].cache_tag[j] ) == i ) {
             phys_qc_lines_in_cache++;
             break;
          }
       }
    }
 }
 CPUPut("PHYS (lines/cache) %d/%d\n",
        phys_qc_lines,
        phys_qc_lines_in_cache);

 for( i = 0; i < LINES_PER_CACHE; i++ ) {
    if(  CACHE_INVALID( EMP[cpuNum].cache_tag[i] ) )
       invalid_cache_tags++;
    for( j = 0; j < LINES_PER_CACHE; j++ ) {
       if(  CACHE_PLINE( EMP[cpuNum].cache_tag[i] ) == 
            CACHE_PLINE( EMP[cpuNum].cache_tag[j] ) &&  
            CACHE_VALID( EMP[cpuNum].cache_tag[i] ) &&
            i != j )
          num_repeated_plines++;
    }
 }

 CPUPut("%d repeated lines %d invalid tags, %d lines in cache\n", 
        num_repeated_plines,
        invalid_cache_tags,
        LINES_PER_CACHE );
}

int cache_verify_excl( int cpuNum, PLN pline )
{
   int j;
   if( !PQC_VLINE(EMP[cpuNum].qc_p[pline]) ) {
      return PQC_DIRTY(EMP[cpuNum].qc_p[pline]);
   }
   for( j = 0; j < LINES_PER_CACHE; j++ ) {
      if ( CACHE_PLINE( EMP[cpuNum].cache_tag[j] ) == pline ) {
         return CACHE_EXCL( EMP[cpuNum].cache_tag[j] );
      }
   }
   return 0;
}

int cache_verify_shared( int cpuNum, PLN pline )
{
   int j;
   if( !PQC_VLINE(EMP[cpuNum].qc_p[pline]) ) {
      return PQC_SHARED(EMP[cpuNum].qc_p[pline]);
   }
   for( j = 0; j < LINES_PER_CACHE; j++ ) {
      if ( CACHE_PLINE( EMP[cpuNum].cache_tag[j] ) == pline ) {
         return CACHE_SHARED( EMP[cpuNum].cache_tag[j] );
      }
   }
   return 0;
}

/* XXXX - This is broken **/
/* This is called on a QC miss.  It drives all cache state transitions */
void MPCache_Ref( int cpuNum, 
                  PA pAddr, 
                  VA vAddr, 
                  EmVQCMemState state )
{
   uint line_no = SCACHE_INDEXOF( pAddr );
   register unsigned pline;
   Dir_Entry new_dir_entry;
   int miss_handling_time;

   ASSERT( embra.parallel );
   pline = ADDR2SLINE(pAddr);

   /* We lock the directory entry, and then make ALL quick check, and */
   /* cache tag modifications, including interventions (already done), */
   /* and updates to our own QC */
   new_dir_entry = Directory_Lock(cpuNum, pAddr, vAddr, state);

   /* Set the new line's quick check to the proper, accesible state */
   /* Note that this invalidates phys_info[pline].virt_line */
   /* Since the new entry could be the same as the old ( like on a TLB */
   /* fault) the invalidate happens first */
   /* Also note since at this point we don't know if we have a TLB or a */
   /* cache miss, we can't yet stall the processor. */
   set_qc_state( cpuNum, ADDR2SLINE(vAddr), pline, state );

   if( pline == CACHE_PLINE( EMP[cpuNum].cache_tag[line_no] ) && pline ) {
      /* If permissions match, then this is a real cache hit, and a qc */
      /* miss */ 
      /* By above test cache_tag is valid, so only need to check excl */
      VASSERT( !VQC_SHARED( state ) || 
               CACHE_VALID( EMP[cpuNum].cache_tag[line_no] ) ||
               !pline ,
               ("State %d, line_no %d\n", state, line_no) );
      if( VQC_SHARED( state ) ||
          ( VQC_EXCL( state) && 
            CACHE_EXCL( EMP[cpuNum].cache_tag[line_no] ) ) ) {
         /* real cache hit, vQC miss */
         Directory_Free(cpuNum, pAddr, new_dir_entry);
         return;
      } else {
         /* Upgrade */
         CACHE_SINC( cpuNum, CURRENT_MODE(&EMP[cpuNum]), upgrades );
         /* Remove xfer time */
         miss_handling_time = MEM_CYCLE_TIME - SCACHE_LINE_SIZE/8;
         goto accountingDone;
      }
   }
   CACHE_INC( cpuNum, CURRENT_MODE(&EMP[cpuNum]), i_miss, d_miss, state );
   miss_handling_time = MEM_CYCLE_TIME;

accountingDone:
   
   EMP[cpuNum].cycleCountdown -= miss_handling_time;
   CACHE_INC_BY(cpuNum, CURRENT_MODE(&EMP[cpuNum]), 
                i_stall_cyc, d_stall_cyc, state,
                miss_handling_time );

   /* If there is a previous entry in this line, kick it out */
   if( CACHE_VALID( EMP[cpuNum].cache_tag[line_no] ) ) {
      /* Kick out previous line */
      /* We know that pline_tag[line_no] != pline */
     if (embra.useVQC) 
       set_qc_state( 
                         cpuNum,
                         PQC_VLINE(
                           EMP[cpuNum].qc_p[
                             CACHE_PLINE(
                               EMP[cpuNum].cache_tag[line_no])]),
                         CACHE_PLINE( EMP[cpuNum].cache_tag[line_no] ), 
                         MEM_INVALID );
   
   } else { /* !embra.useVQC */

       set_qc_state( 
                         cpuNum,0,
                         CACHE_PLINE( EMP[cpuNum].cache_tag[line_no] ), 
                         MEM_INVALID );
   }


   /* Update Embra tags */
   if( VQC_SHARED( state ) ) {
      EMP[cpuNum].cache_tag[line_no] = CACHE_SET_SHARED( pline );
   } else {
      ASSERT( VQC_EXCL( state ) );
      EMP[cpuNum].cache_tag[line_no] = CACHE_SET_EXCL( pline );
   }
   /* Free up the directory entry */
   Directory_Free(cpuNum, pAddr, new_dir_entry);
}