/*
 * Copyright (C) 1996-1998 by the Board of Trustees
 *    of Leland Stanford Junior University.
 * 
 * This file is part of the SimOS distribution. 
 * See LICENSE file for terms of the license. 
 *
 */

#include <bstring.h>
#include <sys/signal.h>
#include "gdb_interface.h"
#include "mips_gdb.h"
#include "simmisc.h"
#include "embra.h"
#include "debug.h"
#include "clock.h"
#include "main_run.h"
#include "qc.h"
#include "driver.h"
#include "mem_control.h"
#include "tcl_init.h"
#include "tc.h"
#include "cp0.h"
#include "machine_params.h"


/* Known Bugs: If you enter debugger when processes are in promslave loop */
/* then you won't restart after. 
 */

#define DEBUG 1

#define BREAKPOINT 0x1
#define SINGLESTEP 0x2
#define SIGNAL 0x4
#define INCR_PC 0x8
#define FLUSH_TC 0x10
#define SIDE_EFFECT 0x20

#define SIGNAL_USR 0x2



static struct EmbraDebug {
   uint statusCode;
   int ignoreNextOne;
   int processingAnn;
   int processingGDB;
   SimTime lastDebugCycle[SIM_MAXCPUS];
} embraDebug;


/* ********************************************************
 * EmbraSideEffect is called whenever a change in the machine
 * state (registers, not memory) occured during a callout. 
 * ********************************************************/

void EmbraDebugInit(void)
{
   int i;
   embraDebug.statusCode = 0;
   embraDebug.processingAnn = 0;
   embraDebug.processingGDB = 0;
   for (i=0;i<TOTAL_CPUS;i++) { 
      embraDebug.lastDebugCycle[i] = 0;
   }
}

void EmbraSideEffect(void) 
{
   if (embraDebug.processingAnn) { 
      embraDebug.statusCode |= SIDE_EFFECT;
   }
}

void EmbraDebug( int cpuNum )
{
   int incrpc = embraDebug.statusCode & INCR_PC;
   
   ASSERT( embra.sequential);
   Simdebug_run(((embraDebug.statusCode & BREAKPOINT) ? 
                       SIGTRAP : SIGUSR2 ),
                      cpuNum);
   if (embraDebug.processingAnn ) { 
      /*
       * finish the annotation first, then
       * check for side-effects,...
       */
      return;
   }
   if (embraDebug.processingGDB) { 
      FlushTCIfNecessary(cpuNum);
      if( incrpc ) {
         EMP[cpuNum].PC += INST_SIZE;
      } 
      ASSERT( (EMP[cpuNum].PC & 0x3) == 0 );
      embraDebug.statusCode &= ~SIDE_EFFECT;
      embraDebug.processingGDB = 0;
      ReenterTC( &EMP[cpuNum] );
      /* NOT REACHED */
      return;
   }             
}

void FlushTCIfNecessary(int cpuNum)
{
   if( embraDebug.statusCode & FLUSH_TC ) {
      /* 
       *this bit might get set in Simdebug_run 
       */

      /* The following call does not work for
       * MPinMP.  However, MPinUP ignores the
       * cpuNum argument so it is fine.
       *
       * Problem is that debugger could have modified
       * stuff that is in any cpu, so we need to
       * flush stuff across the board.
       */

      Clear_Translation_State( TCFLUSH_ALL);
      embraDebug.statusCode &=~FLUSH_TC;
   }
}


int EmbraAnnType(void)
{
   return embraDebug.processingAnn;
}



/* **************************************************************
 * Embra_Handle_Debug_Signal
 * 
 * Called through CPUVec in the case of a debug annotation
 * and in the case of a SIGUSR1
 * **************************************************************/


void Embra_Handle_Debug_Signal( int cpuid, int sigusr )
{
  /*
   * Handle the debugging or the signal synchronously
   * However, we need to make sure that time has advanced,
   * else, we will go into an infinite loop. 
   * Annotations that are on the same pc/mem location will
   * be executed twice, with the exception of the debugging
   * interaction (that ocurs once). 
   * 
   * This is required since we need to do a ReenterTC after
   * the debugging interaction. 
   */


   /* Check this value when we drop into debugger, it allows us to set the embraDebug.statusCode */
   int cpu = (cpuid<0?CPUVec.CurrentCpuNum():cpuid);
   ASSERT( cpu >= 0 && cpu < TOTAL_CPUS);

   if (sigusr) {
      embraDebug.statusCode = SIGNAL_USR;
   } else { 
      /*
       * process the debugging requests immediately
       */
      EmbraDebug(cpu);
   }
}


/* This gets called from a kernel breakpoint */
void Embra_SimosKernDebugBreak( int cpuNum )
{
   ASSERT (curEmp->myNum == cpuNum);
   CPUWarning("DEBUGGER at %#x\n",EMP[cpuNum].PC);
   embraDebug.statusCode = 0;
   embraDebug.statusCode |= BREAKPOINT;
   embraDebug.statusCode |= INCR_PC;   /* Kernel breakpoints are stepped over */
   embraDebug.processingGDB = 1;
   EmbraDebug(cpuNum);
}

/* 
 * this gets from a breakpoint too. Used to step. 
 */

void Embra_SimosDebugBreak( int cpuNum )
{
   ASSERT (curEmp->myNum == cpuNum);
   CPUWarning("DEBUG: Debug break\n");
   if( embraDebug.lastDebugCycle[cpuNum]== EmbraCpuCycleCount( cpuNum ) ) {
      /* prevent infinite loop 
       * This is our way of stepping over the code that calls the annotation
       * by disabling it the next time around.
       * Catch: any other annotations installed at the same PC 
       * will be called twice.
       */
      CPUWarning("Embra_SimosDebugBreak: skip \n");
      return;
   }
   embraDebug.lastDebugCycle[cpuNum] = EmbraCpuCycleCount( cpuNum );
   embraDebug.statusCode = 0;
   embraDebug.statusCode |= BREAKPOINT;
   embraDebug.processingGDB = 1;
   EmbraDebug(cpuNum);
}


/* No one returns from this procedure */
/* We leave via the execption path */
/* This insures that if we wrote registers, our register allocaiton in */
/* translation won't break */



/* *****************************************************************
 * EmbraPollSigUsr. 
 * the last thing we want to do is to interpret Tcl scripts on the 
 * signal stack. Called from the periodic callout 
 * *****************************************************************/


void EmbraPollSigUsr( int cpuNum )
{
   
   if (embraDebug.statusCode & SIGNAL_USR) {
      embraDebug.statusCode &= ~SIGNAL_USR;
      AnnExec(AnnFind("simos", "sigusr"));
   }
}


/* **************************************************************
 * EmbraAnnExec
 * 
 * returns unless the annotation has a side-effect on the machine
 * state.
 * 
 * XXX Known limitiation: if the tcl script has side-effects and
 * the PC is in a delay slot, we are hosed!!! (for now)
 *
 * **************************************************************/

void EmbraAnnExec(int cpuNum,AnnPtr ptr, int annType)
{
   VA pc = EMP[cpuNum].PC;
   ASSERT (!embraDebug.processingAnn);
   ASSERT (annType);
   if (embraDebug.ignoreNextOne) { 
      embraDebug.ignoreNextOne = 0;
      if (DEBUG) { 
         CPUWarning("EmbraAnnExec: skipping annotation \n");
      }
      return;
   }
   embraDebug.statusCode &= ~(SIDE_EFFECT|FLUSH_TC);
   embraDebug.processingAnn = annType;
   AnnExec(ptr);
   embraDebug.processingAnn = 0;
   if (embraDebug.statusCode & FLUSH_TC) { 
      ASSERT (embraDebug.statusCode & SIDE_EFFECT);
      Clear_Translation_State( TCFLUSH_ALL);
   }
   if (embraDebug.statusCode & SIDE_EFFECT) {
      if (annType==ANNFM_LD_TYPE ||
          annType==ANNFM_ST_TYPE ||
          annType==ANNFM_PRE_PC_TYPE) { 
         if (EMP[cpuNum].PC == pc) { 
            embraDebug.ignoreNextOne = 1;
         }
      } else { 
         ASSERT (annType==ANNFM_PC_TYPE);
         if (EMP[cpuNum].PC ==pc) { 
            /*
             * there we better skip the instruction
             * as some are not idempotent.
             */
            ASSERT( !IN_BD(EMP[cpuNum].PC));
            EMP[cpuNum].PC += INST_SIZE;
            EMP[cpuNum].cycleCountdown--;
         }
      }
      ASSERT( !IN_BD(EMP[cpuNum].PC));
      ReenterTC(&EMP[cpuNum]);
      /* NOTREACHED */
   }
   embraDebug.statusCode &= ~FLUSH_TC;
   embraDebug.statusCode &= ~SIDE_EFFECT;
}
   

/* **************************************************************
 * Callbacks during the gdb session. These have side-effects on
 * embraDebug.statusCode 
 * *************************************************************/


Result Embra_GetRegister(int cpuNum, int regnum, Reg *val)
{
   EmbraState* P = &EMP[cpuNum];

   if (regnum < 0) { 
      return FAILURE;
   }
   
   if (regnum <= RA_REGNUM) {
      *val = P->R[regnum];
      return SUCCESS;
   }
   
   if ((regnum >= FP0_REGNUM) && (regnum < FP0_REGNUM+32))  {
      *val = P->FPR[regnum-FP0_REGNUM];
      return SUCCESS;
   }
   
   switch (regnum) {
   case LO_REGNUM: *val =  P->LO;   break;
   case HI_REGNUM: *val =  P->HI;   break;
   case PC_REGNUM: *val = CLEAR_BD(P->PC); break;
   case FCRCS_REGNUM: *val =  P->FCR[31];   break;
   case FCRIR_REGNUM: *val =  P->FCR[30];   break;
   case INX_REGNUM: *val =  P->CP0[C0_INX];   break;
   case RAND_REGNUM: *val =  P->CP0[C0_RAND];   break;
   case TLBLO_REGNUM: *val =  P->CP0[C0_TLBLO_0];   break;
   case CTXT_REGNUM: *val =  P->CP0[C0_CTXT];   break;
   case TLBHI_REGNUM: *val =  P->CP0[C0_TLBHI];   break;
   case SR_REGNUM: *val =  P->CP0[C0_SR];   break;
   case EPC_REGNUM: *val =  P->CP0[C0_EPC];   break;
   case ERROR_EPC_REGNUM: *val =  P->CP0[C0_ERROR_EPC];   break;
   case PRID_REGNUM: *val =  P->CP0[C0_PRID];   break;
   case CAUSE_REGNUM: *val = P->CP0[C0_CAUSE];  break;
   case BAD_REGNUM:   *val = P->CP0[C0_BADVADDR]; break;
   case COUNT_REGNUM:    *val = P->CP0[C0_COUNT];       break;
   case COMPARE_REGNUM:  *val = P->CP0[C0_COMPARE];       break;
   case TLBLO1_REGNUM:   *val = P->CP0[C0_TLBLO_1];       break;
   case PGMASK_REGNUM:   *val = P->CP0[C0_PGMASK];       break;
      
   default:
      return FAILURE;
   }
   
   return SUCCESS;
}


Result Embra_PutRegister(int cpuNum, int regnum, Reg val)
{
   EmbraState* P = &EMP[cpuNum];
   if (embraDebug.processingAnn == ANNFM_LD_TYPE ||
       embraDebug.processingAnn == ANNFM_ST_TYPE) { 
      embraDebug.statusCode |= SIDE_EFFECT;
   } else {
      ASSERT(!embraDebug.processingAnn ||
             embraDebug.processingAnn==ANNFM_PC_TYPE ||
             embraDebug.processingAnn==ANNFM_PRE_PC_TYPE);
   }

   if ((regnum < 0) || (regnum >= GDB_NUM_REGS)) {
      return FAILURE;
   }
   
   if (regnum <= RA_REGNUM)  {
      P->R[regnum] = val;
      return SUCCESS;
   }
   
   if ((regnum >= FP0_REGNUM) && (regnum < FP0_REGNUM+32))  {
      P->FPR[regnum-FP0_REGNUM] = val;
      return SUCCESS;
   }

   /*
    * for those, assume a side-effect, even from a pc annotation
    */
   embraDebug.statusCode |= SIDE_EFFECT;

   switch (regnum) {
   case LO_REGNUM: P->LO = val;  break;
   case HI_REGNUM: P->HI = val;  break;
   case PC_REGNUM: P->PC = val;  break;
   case FCRCS_REGNUM: P->FCR[31] = val;  break;
   case FCRIR_REGNUM: P->FCR[30] = val;  break;
   case INX_REGNUM: P->CP0[C0_INX] = val;  break;
   case RAND_REGNUM: P->CP0[C0_RAND] = val;  break;
   case TLBLO_REGNUM: P->CP0[C0_TLBLO_0] = val;  break;
   case CTXT_REGNUM: P->CP0[C0_CTXT] = val;  break;
   case TLBHI_REGNUM: P->CP0[C0_TLBHI] = val;  break;
   case SR_REGNUM: P->CP0[C0_SR] = val;  break;
   case EPC_REGNUM: P->CP0[C0_EPC] = val;  break;
   case ERROR_EPC_REGNUM: P->CP0[C0_ERROR_EPC] = val;  break;
   case PRID_REGNUM: P->CP0[C0_PRID] = val;  break;
   case CAUSE_REGNUM:  P->CP0[C0_CAUSE] = val;  break;
   case BAD_REGNUM:    P->CP0[C0_BADVADDR] = val; break;
   case COUNT_REGNUM:    P->CP0[C0_COUNT]      = val; break;
   case COMPARE_REGNUM:  P->CP0[C0_COMPARE]    = val; break;
   case TLBLO1_REGNUM:   P->CP0[C0_TLBLO_1]    = val; break;
   case PGMASK_REGNUM:   P->CP0[C0_PGMASK]     = val; break;

   default: 
     return FAILURE;
   }
   return SUCCESS;
}

/* static */
K0A debug_non_excepting_tv( int cpuNum, VA vAddr)
{
   MA mAddr;
   PA pAddr;
   int machine = M_FROM_CPU(cpuNum);
   
   if (IS_BACKDOOR(vAddr)) {
      return 0;
   }
   if (!EMP[cpuNum].mmu) {
      CPUWarning("\n\nEMBRA: non_excepting_tc called before init\n\n");
      return 0;
   }

   /* KSEG0 addresses don't have to go through the mmu in the
    * debugger. We don't care about the firewall, or about whether a
    * translation is in the mmu or not. We have to be sure to do
    * the remapping, tho.
    */
   if (IS_CKSEG0(vAddr) && IS_VALID_PA(machine, K0_TO_PHYS(vAddr)))
      return PHYS_TO_K0(K0_TO_PHYS_REMAP(vAddr, cpuNum));
   
#if defined(SIM_MIPS64)
   if (IS_XKPHYS(vAddr) && IS_VALID_PA(machine, XKPHYS_TO_PHYS(vAddr)))
     return PHYS_TO_K0(K0_TO_PHYS_REMAP(vAddr, cpuNum));
#endif

#ifdef EMBRA_USE_QC64
   mAddr = (MA)((VA)Em_QC64Reload(vAddr,0) & ~(DEFAULT_PAGESZ-1));
#else
   mAddr = EMP[cpuNum].mmu[PAGE_NUMBER(vAddr)];
#endif
   
   if (!mAddr && IS_KSEG0(vAddr)) {
      ASSERT( IS_VALID_PA(machine, K0_TO_PHYS(vAddr)));
      return vAddr;
   }

   if (!mAddr) { 
      int indx = Tlb_Lookup(cpuNum, GET_REGION(vAddr), GET_VPN2(vAddr),
                            CURRENT_ASID(cpuNum));
      if (indx) {
         Reg lo_reg;
         PA pAddr;

#ifdef SIM_MIPS64
         int szEntry = curEmp->tlbEntrySize[indx-1];
	 int way = !(vAddr & PgSz[szEntry].loBit);
#else
	 int way = IS_LO_0(PAGE_NUMBER(vAddr));
#endif
	 if (way) { 
            lo_reg = EMP[cpuNum].tlbEntry[indx-1].Lo0;
         } else {
            lo_reg = EMP[cpuNum].tlbEntry[indx-1].Lo1;
         }
         if (IS_VALID(lo_reg)) {
#ifdef SIM_MIPS64
#define SZ2MASK(_s) PgSz[(_s)].mask
	   pAddr = (((GET_PFN(lo_reg)&SZ2MASK(szEntry))*4*1024) | 
               (vAddr & PgSz[szEntry].offset_mask));

#else
            pAddr = FORM_ADDR(GET_PFN(lo_reg),  PAGE_OFFSET(vAddr));
#endif
            ASSERT(IS_VALID_PA(machine, pAddr));
            return PHYS_TO_K0(pAddr);
         }
      }
   }

   if (!mAddr) {
      /* We couldn't translate the virtual address using anything in the 
       * hardware. Callout to tcl to walk the OS data structures.
       */
      if (pAddr = TclTranslateVirtual(cpuNum, vAddr)) {
         ASSERT(IS_VALID_PA(machine, pAddr));
         return PHYS_TO_K0(pAddr);
      }
   }

   if (mAddr) {
       mAddr += PAGE_OFFSET( vAddr );
      /* Only needed for page mode, but instead of checking its */
      /* cheaper to just do it */ 
       ASSERT(IS_VALID_PA(machine, MEMADDR_TO_PHYS(machine, MMU2ADDR(mAddr))));
      return MEMADDR_TO_K0(machine, MMU2ADDR(mAddr));
   }

   return 0;
}

Result Embra_GetMemory(int cpuNum, VA vAddr, uint nbytes, char *buf)
{
   int machine = M_FROM_CPU(cpuNum);
   K0A k0Addr = debug_non_excepting_tv(cpuNum, vAddr);
   PA pAddr;
   if (!k0Addr) {
      return FAILURE;
   }
   ASSERT( IS_KSEG0(k0Addr));
   pAddr = K0_TO_PHYS(k0Addr);

   ASSERT(IS_VALID_PA(machine, pAddr));
   
   if (PAGE_NUMBER(vAddr + nbytes - 1) == PAGE_NUMBER(vAddr)) {
      /* entire range fits on a page */

      bcopy((void*)PHYS_TO_MEMADDR(machine,pAddr), buf, nbytes);

   } else {
      int bytes_on_first_page = (1 << NUM_OFFSET_BITS) - PAGE_OFFSET(vAddr);
      VA vAddr2 = ((VA) vAddr) + bytes_on_first_page;
      K0A k0Addr2 = debug_non_excepting_tv(cpuNum, vAddr2);
      PA pAddr2 = K0_TO_PHYS(k0Addr2);

      ASSERT(nbytes <= (1 << NUM_OFFSET_BITS));
      
      if (!k0Addr2) {
         return FAILURE;
      }
      ASSERT( IS_KSEG0(k0Addr2));
      ASSERT(IS_VALID_PA(machine, pAddr));
      
      bcopy(PHYS_TO_MEMADDR(machine, pAddr),
            buf, bytes_on_first_page);
      bcopy(PHYS_TO_MEMADDR(machine, pAddr2), 
            ((void*)((unsigned)buf + bytes_on_first_page)), 
            nbytes - bytes_on_first_page);
   }

   return SUCCESS;
}

Result Embra_PutMemory(int cpuNum, VA vAddr, uint nbytes, char *buf)
{
   K0A k0Addr = debug_non_excepting_tv(cpuNum, vAddr);
   embraDebug.statusCode |= SIDE_EFFECT;

   if (!k0Addr) {
      return FAILURE;
   }
   
   if (PAGE_NUMBER(vAddr + nbytes - 1) == PAGE_NUMBER(vAddr)) {
      /* entire range fits on a page */
      if (buf != (char*) K0_TO_MEMADDR(M_FROM_CPU(cpuNum), k0Addr))
         bcopy( buf, (void*)K0_TO_MEMADDR(M_FROM_CPU(cpuNum), k0Addr), nbytes);
      embraDebug.statusCode |= FLUSH_TC;

   } else {
      int bytes_on_first_page = (1 << NUM_OFFSET_BITS) - PAGE_OFFSET(vAddr);
      VA vAddr2 = ((VA) vAddr) + bytes_on_first_page;
      K0A k0Addr2 = debug_non_excepting_tv(cpuNum, vAddr2);

      ASSERT(nbytes <= (1 << NUM_OFFSET_BITS));
      
      if (!k0Addr2) {
         return FAILURE;
      }
      
      bcopy(buf, (void*)K0_TO_MEMADDR(M_FROM_CPU(cpuNum), k0Addr),
            bytes_on_first_page);
      bcopy(((void*)((unsigned)buf + bytes_on_first_page)), 
            (void*) K0_TO_MEMADDR(M_FROM_CPU(cpuNum), k0Addr2), 
            nbytes - bytes_on_first_page );
      embraDebug.statusCode |= FLUSH_TC;
   }

   return SUCCESS;
}

Result Embra_TranslateVirtualNoSE(int cpuNum, VA vAddr, PA *pAddr)
{
   K0A k0A = debug_non_excepting_tv(cpuNum,vAddr);
   if (k0A) {
      *pAddr = K0_TO_PHYS(k0A);
      return SUCCESS;
   } else {
      return FAILURE;
   }
}