/*
 * Copyright (C) 1996-1998 by the Board of Trustees
 *    of Leland Stanford Junior University.
 * 
 * This file is part of the SimOS distribution. 
 * See LICENSE file for terms of the license. 
 *
 */

/****************************************************************
 * qc64.c
 *
 * This file handles the quickcheck and Physarray structures.
 * pa/phys_mem_ref gets called in case of callout from the 
 * Translation Cache
 * 
 * $Author: blythe $
 * $Date: 2002/05/29 01:09:10 $
 *****************************************************************/
#include <stdio.h>
#include <sys/types.h>
#include <sys/stat.h>
#include <sys/mman.h>
#include <fcntl.h>
#include <bstring.h>
#include <string.h>
#include <assert.h>
#include "simmisc.h"
#include "embra.h"
#include "cache.h"
#include "qc.h"
#include "stats.h"
#include "driver.h"
#include "clock.h"
#include "mem_control.h"
#include "main_run.h"
#include "cp0.h"
#include "annotations.h"
#include "simutil.h"
#include "machine_defs.h"
#include "firewall.h"
#include "simmagic.h"
#include "tc.h"
#include "tc_coherence.h"
#include "simtypes.h"

#ifdef EMBRA_USE_QC64
void qc_CheckForDuplicates(CPUState *P);

static struct {
   VA   vpn_mask;     /* VPN mask for a TLB entry */
   int  page_count;   /* Number of 4K pages mapped by a TLB entry */
   int offset_mask;   /* Page offset mask. */
} TlbEntrySz[TLBPGMASK_NUMSIZES] = {
   { ~(((TLBPGMASK_4K>>13)<<1)|1),   (2*4*1024)/DEFAULT_PAGESZ,     4*1024-1},
   { ~(((TLBPGMASK_16K>>13)<<1)|1),   (2*16*1024)/DEFAULT_PAGESZ,    16*1024-1},
   { ~(((TLBPGMASK_64K>>13)<<1)|1),   (2*64*1024)/DEFAULT_PAGESZ,    64*1024-1},
   { ~(((TLBPGMASK_256K>>13)<<1)|1), (2*256*1024)/DEFAULT_PAGESZ,   256*1024-1}, 
   { ~(((TLBPGMASK_1M>>13)<<1)|1),  (2*1024*1024)/DEFAULT_PAGESZ,  1024*1024-1},
   { ~(((TLBPGMASK_4M>>13)<<1)|1),   (2*4*1024*1024)/DEFAULT_PAGESZ, 4*1024*1024-1},
   { ~(((TLBPGMASK_16M>>13)<<1)|1), (2*16*1024*1024)/DEFAULT_PAGESZ,16*1024*1024-1},
};

#define IS_KERNEL_ONLY_ADDR(_va) (((Reg64_s)(_va)) < 0)
#define ANY_HIGH32_BITS(_va)     ((_va)>>32)

extern int (*QC64HashFunc)(VA vAddr);
static void QC64Check(EmbraState *P, int myASID);

/*
 * ReinitQC64(EmbraState *P) - Reinitialize the QC64 hash table
 * and backmapping table. 
 */
static void 
ReinitQC64(EmbraState *P)
{
    int i;
    for (i = 0; i < QC64_NUM_ENTRIES; i++) {
       P->kernelMMU[i].vpn = QC64_INVALID_VPN;
       P->userMMU[i].vpn = QC64_INVALID_VPN;
    }
    for (i = 0; i < MAX_NTLBENTRIES; i++) { 
      P->QC64TLBBackMap[i] = QC64_INVALID_VPN;
    }
}


/*
 * AddAddrQC64() Add an vAddr -> MA mapping to the QC64
 */

static void
AddAddrQC64(EmbraState *P, VA vAddr, MA ma, int writable)
{
   int hash;
   hash =  QC64HashFunc(vAddr);

   ma =  (MA) ((uint)ma & ~(DEFAULT_PAGESZ-1));
   P->kernelMMU[hash].vpn = vAddr/DEFAULT_PAGESZ;
   P->kernelMMU[hash].ma = ma;
   P->kernelMMU[hash].writable = writable;
  
   if (!IS_KERNEL_ONLY_ADDR(vAddr)) { 
      P->userMMU[hash].vpn = vAddr/DEFAULT_PAGESZ;
      P->userMMU[hash].ma = ma;
      P->userMMU[hash].writable = writable;
   }
}

/*
 * RemoveAddrQC64(EmbraState *P, VA vAddr) - Remove an
 * address from the QC64.
 */
static void
RemoveAddrQC64(EmbraState *P, VA vAddr)
{
   int hash =  QC64HashFunc(vAddr);
   if (P->kernelMMU[hash].vpn == vAddr/DEFAULT_PAGESZ) { 
      P->kernelMMU[hash].vpn =  QC64_INVALID_VPN;
   }
   if (P->userMMU[hash].vpn ==  vAddr/DEFAULT_PAGESZ) { 
      P->userMMU[hash].vpn =  QC64_INVALID_VPN;
   }
}

/*
 * FlushTLBEntryQC64 - Remove the specified TLB entry from the
 * QC64.
 */
static void 
FlushTLBEntryQC64(EmbraState *P, int idx)
{
   int hash, i;
   VA vpn =   P->QC64TLBBackMap[idx];

    if (vpn != QC64_INVALID_VPN) { 
       int kernelOnly = IS_KERNEL_ONLY_ADDR(vpn*DEFAULT_PAGESZ);
       int size =  P->tlbEntrySize[idx];

       /* Must remove all the default (4K) pages that make
        * up this page */
       vpn = vpn & TlbEntrySz[size].vpn_mask;
       for (i = 0; i < TlbEntrySz[size].page_count; i++) { 
          hash =  QC64HashFunc(vpn*DEFAULT_PAGESZ + i*DEFAULT_PAGESZ);
          P->kernelMMU[hash].vpn = QC64_INVALID_VPN;
          if (!kernelOnly) { 
             P->userMMU[hash].vpn = QC64_INVALID_VPN;
          }
       }
    }
    P->QC64TLBBackMap[idx] = QC64_INVALID_VPN;
}



static void 
InitQC64(void)
{

   int cpu;

   assert( embra.sequential);

   for( cpu = 0; cpu < TOTAL_CPUS; cpu++ ) {

      if (EMP[cpu].mmu) continue;

      EMP[cpu].kernelMMU = (QC64HashEntry *) 
         malloc(sizeof(QC64HashEntry)*QC64_NUM_ENTRIES);

      EMP[cpu].mmu = EMP[cpu].kernelMMU;
      if (embra.separateMMUs) { 
            EMP[cpu].userMMU = 
               malloc(sizeof(QC64HashEntry)*QC64_NUM_ENTRIES);
      } else { 
            EMP[cpu].userMMU = EMP[cpu].kernelMMU;
      }
      EMP[cpu].QC64TLBBackMap = (VA *) malloc(MAX_NTLBENTRIES*sizeof(VA));
      ReinitQC64(EMP + cpu);
   }


   /* Page mode doesn't use quick checks */
   if( embra.emode == EMBRA_PAGE )
      return;
   ASSERT(!embra.useVQC);

   for( cpu = 0; cpu < TOTAL_CPUS; cpu++ ) {
      /* Record QC_V reloc base */
      if (EMP[cpu].pa_p) continue;
      EMP[cpu].pa_p = (pa_info_t*) ZALLOC_PERM(PA_SIZE(M_FROM_CPU(cpu)),"EmbraPA");
	 /* memory access entry holds value for PA_REG */
      EMP[cpu].cache_ax=(pa_info_t *)(EMP[cpu].pa_p-
                                      (MA_TO_UINT(SIM_MEM_ADDR(M_FROM_CPU(cpu))) >> 
                                       log2SCACHE_LINE_SIZE));
   }

}

/* Invalidate the quick check entries specified in cpu_bits */
/* Invalidate physical first to avoid race condition */
void 
qc_clobber( PA pAddr, int cpuNum, EmVQCMemState state )
{

  EMP[cpuNum].pa_p[ADDR2SLINE(pAddr)] = PA_SET_INV; 

}

void
qc64_remove_addr(int cpuNum, VA va)
{
   RemoveAddrQC64(&EMP[cpuNum], va);
}

/* Transition from exclusive to read shared -- used when newly written */
/* code is executed.  This allows us to detect further writes */
void qc_downgrade(int cpuNum, VA vAddr, int new_state)
{

  ASSERT( VQC_SHARED(new_state) );
  RemoveAddrQC64(&EMP[cpuNum], vAddr);
}

/* *************************************************************
 * for all cpus, downgrade the protection. called by
 * icache_coherence_mark_code
 * *************************************************************/

void qc_downgrade_ifpresent(VA vAddr)
{
   int cpuNum;
   for (cpuNum = 0; cpuNum < TOTAL_CPUS; cpuNum++) {
      RemoveAddrQC64(&EMP[cpuNum], vAddr);
   }
}



/* Page mode: note that driver.c:EmbraInstallMemAnnotation will be
 * called after qc_renew runs, so we are free to put in translations
 * here for all pages, even those with load/store annotations on them.  
 */
void 
qc_renew( int cpuNum )
{
  if( !embra.MPinUP || cpuNum == 0 ) InitQC64();

  ReinitQC64(EMP + cpuNum);
  Clear_Translation_State( TCFLUSH_ALL);

} 


/*
 * Em_QC64Reload - Handle the reloading the QC64 on a 
 * miss. Returns 0 if QC wasn't filled.
 */
MA
Em_QC64Reload(VA vAddr, int flags )
{
  int          myASID, region, hashNum, idx;
  PA          pAddr;
  Reg         VPN2, lo_reg;
  Reg32      sr_reg;
  List_Links* indexPtr;
  EmbraState   *P;
  int         writeable = 0;
  MA          ma;

   P  = curEmp;
   sr_reg = (Reg32)(P->CP0[C0_SR]);
   region = GET_REGION(vAddr);

   if (region == 0) { 
      /* User region access */
      if (!(sr_reg & SR_UX) && ANY_HIGH32_BITS(vAddr)) return 0;
      /* Fall thru to TLB lookup */
   } else if (region == 2) {
      /* xkphys access */
      uint cache_algorithm = XKPHYS_CACHE_ALGORITHM(vAddr);
      /* xkphys - only available in kernel 64bit mode */
      if (!IS_KERNEL_MODE(P) || !(sr_reg & SR_KX)) return 0;
      /* Currently we only support EXCLUSIVE_WRITE access quick check */
      if (cache_algorithm == CBIT_EXCLUSIVE_WRITE) {
         pAddr = K0_TO_PHYS_REMAP(vAddr, P->myNum);
         writeable = 1; 
         idx = -1;
         goto checkAccess;
      }
      return 0;
   } else if (region == 3) {
      /* Kernel region, no user and limited supervisor */
      if (vAddr >= CKSEG0_START_ADDR) {
         if (!IS_KERNEL_MODE(P)) {
            /* No user and supervisor limited to single range */
            if (IS_BACKDOOR(vAddr) || (sr_reg & SR_KSU_USR) ||
                ((sr_reg & SR_KSU_SUP) && !IS_SUPERV_SEG(vAddr))) return 0;
         }
         if (IS_KSEG0(vAddr)) {
            if (!IS_KERNEL_MODE(P)) return 0; /* Kernel only */
#ifndef TORNADO
            if (remapVec->RemapEnable[P->myNum] &&
                (vAddr >= __MAGIC_OSPC_BASE && vAddr < __MAGIC_OSPC_END)) {
               return 0;
            }
#endif
            pAddr = K0_TO_PHYS_REMAP(vAddr, P->myNum);
            idx = -1;
            writeable = 1; 
            goto checkAccess;
         }
         if (IS_KSEG1(vAddr)) return 0;
         /* Fall thru to TLB lookup */
      } else { 
         /* If we got here we better not be in 32bit mode and
          * there is nothing that the user or supvisor can access.
          */
         if (!(sr_reg & SR_KX) || !IS_KERNEL_MODE(P)) return 0;
      }
      /* Fall thru to TLB lookup */

   } else if (region == 1) {
      /* Supervisor region - only available in 64bit mode */
      if (!(sr_reg & SR_SX) || ((sr_reg & SR_KSU_USR) && !IS_KERNEL_MODE(P)))
             return 0;
      /* Fall thru to TLB lookup */
   }

    /* Check TLB assuming first a 16K page then a 4K page */
    VPN2 = GET_VPN2(vAddr);
    myASID = GET_ASID(P->CP0[C0_TLBHI]); 
    idx = Tlb_Lookup( P->myNum, region, VPN2, myASID );
   
    if (idx) {
      int szEntry; 
      idx--;
      /* We have a matching VPN and ASID - see if it is valid */
      szEntry = P->tlbEntrySize[idx];
      /* Which lo register? */
      if (vAddr & (TlbEntrySz[szEntry].offset_mask+1))
         lo_reg = P->tlbEntry[idx].Lo1;
      else
         lo_reg = P->tlbEntry[idx].Lo0;
      
      if (IS_VALID(lo_reg) && ( IS_DIRTY(lo_reg) || !(flags & QC64_WRITE))) {
            /* Everything is cool - form the address */
         pAddr = ((((GET_PFN(lo_reg)))*DEFAULT_PAGESZ) & 
                  ~(VA)TlbEntrySz[szEntry].offset_mask) + 
            (vAddr & TlbEntrySz[szEntry].offset_mask);
         writeable = IS_DIRTY(lo_reg);
         goto checkAccess;
      }
    }
   /* Missed in TLB */
   return 0;

  
  checkAccess: 
   if (!IS_VALID_PA(M_FROM_CPU(P->myNum), pAddr)) {
      ASSERT(0);
      return 0;
   }
#ifdef BROKEN
   if (SIMFIREWALL_ON) { 
     if (SimMagic_IsIncoherent(pAddr)) return 0;
     if (!CheckFirewall(P->myNum, pAddr)) {
        if (flags & QC64_WRITE) return 0;
        writeable = 0;
     }
   }
#endif
  if (annWatchpoints && 
      AnnFMRangeCheck(vAddr,ANNFM_LD_TYPE|ANNFM_ST_TYPE)) return 0;

   ma = PHYS_TO_MEMADDR(M_FROM_CPU(P->myNum),pAddr); 
   if ( writeable
        && (flags&QC64_WRITE)
        && EmbraTCCoherenceCheck(P->myNum,vAddr,
                                 (pAddr&~(DEFAULT_PAGESZ-1)),
                                 (pAddr&~(DEFAULT_PAGESZ-1))+DEFAULT_PAGESZ)) {
      AddAddrQC64(P,vAddr, ma, 0);
      if (idx >= 0) { 
         P->QC64TLBBackMap[idx] = vAddr/DEFAULT_PAGESZ;
      }
#if 0
      CPUWarning("Flushing the TC in Em_QC64Reload (TC coherence) PC=0x%llx vAddr=0x%llx \n",
                 (Reg64)P->PC, (Reg64)vAddr);
#endif
      ReenterTC(P);
      /* NOTREACHED() */
   }
   if (writeable && TCcoherence_is_code(PHYS_TO_MEMADDR(M_FROM_CPU(P->myNum), pAddr))) {
      writeable = 0;
   }
                                  
    AddAddrQC64(P,vAddr, ma, writeable);

    if (idx >= 0) { 
       P->QC64TLBBackMap[idx] = vAddr/DEFAULT_PAGESZ;
    }
   return ma;
}

void qc_tlb_inval_page( int cpuNum, int idx)
{
   EmbraState *P = EMP + cpuNum;
   EntryHi hi = P->tlbEntry[idx].Hi;

   if( !IS_UNMAPPED_TLBHI( hi ) ) {
      FlushTLBEntryQC64(&EMP[cpuNum], idx);  
   }


}

void qc_tlb_replace_page( int cpuNum, int idx)
{
   qc_tlb_inval_page( cpuNum, idx);
}


void qc_cache_inval_page( int cpuNum, int idx )
{
  ASSERT( embra.emode == EMBRA_CACHE );
  /* No dothing */
  
}


/* Always invalidate the previous virtual line.  That way, physical */
/* entries are aliased only once */
void set_qc_state( int cpuNum, VLN vline, PLN pline, int new_state )
{
   PA pAddr = SLINE2ADDR(pline);
#ifdef BROKEN
  ASSERT(!SIMFIREWALL_ON);  /* this function doesn't support the firewall yet*/
#endif
  /* WATCHPOINTS */
  if (annWatchpoints == TRUE) {
     if (AnnFMRangeCheck(vline << log2SCACHE_LINE_SIZE,
                         ANNFM_LD_TYPE | ANNFM_ST_TYPE)) {
        new_state = MEM_INVALID;
     }
  }
  if (new_state==MEM_D_EXCLUSIVE &&
      TCcoherence_is_code(PHYS_TO_MEMADDR(M_FROM_CPU(cpuNum), pAddr))) {
     new_state = MEM_D_SHARED;
  }
  
   switch( new_state ) {
    case MEM_INVALID: 
      EMP[cpuNum].pa_p[pline] = PA_SET_INV;
      break;
    case MEM_D_EXCLUSIVE:
    case MEM_I_EXCLUSIVE:
      EMP[cpuNum].pa_p[pline] = PA_SET_DIRTY;
      break;
    case MEM_I_SHARED:
    case MEM_D_SHARED:
      EMP[cpuNum].pa_p[pline] = PA_SET_SHARED;
      break;
    }

}


/* XXX - Caller check ASID and/or global bit */
void qc_cache_reload_page( int cpuNum, VA vLine, EntryLo lo0, EntryLo lo1)
{
   PA pLine;
/* Need to modify for multiple page sizes */
   if( IS_VALID(lo0) ) {
     for( pLine = ADDR2SLINE(TLBLO2ADDR(lo0)); 
          pLine < ADDR2SLINE(TLBLO2ADDR(lo0)) + LINES_PER_PAGE; 
          pLine++, vLine++ ) {
       uint tag = EMP[cpuNum].cache_tag[SCACHE_INDEXOF(SLINE2ADDR(pLine))];
       if( CACHE_VALID( tag ) && CACHE_PLINE( tag ) == pLine ) {
         if( CACHE_EXCL( tag ) && IS_DIRTY(lo0) ) {
           set_qc_state(cpuNum, vLine, pLine, MEM_D_EXCLUSIVE);
         } else {
           /* Don't know I/D */
           set_qc_state(cpuNum, vLine, pLine, MEM_D_SHARED);
         }

       }
     }
   } else { 
      vLine += LINES_PER_PAGE;
   }
   if( IS_VALID(lo1) ) {
     for( pLine = ADDR2SLINE(TLBLO2ADDR(lo1)); 
          pLine < ADDR2SLINE(TLBLO2ADDR(lo1)) + LINES_PER_PAGE; 
          pLine++, vLine++ ) {
       uint tag = EMP[cpuNum].cache_tag[SCACHE_INDEXOF(SLINE2ADDR(pLine))];
       if( CACHE_VALID( tag ) && CACHE_PLINE( tag ) == pLine ) {
         if( CACHE_EXCL( tag ) && IS_DIRTY(lo1) ) {
           set_qc_state(cpuNum, vLine, pLine, MEM_D_EXCLUSIVE);
         } else {
           /* Don't know I/D */
           set_qc_state(cpuNum, vLine, pLine, MEM_D_SHARED);
         }

       }
     }
   }
}

   
void qc_map_page( int cpuNum, int idx)
{
   /* We do this in a lazy way for QC64 */
}

void qc_flush_etlb(int cpuNum)
{
}

void qc_erase_etlb(int cpuNum, EntryHi hi)
{

}

K0A non_excepting_tv( int cpuNum, VA vAddr)
{
   MA mAddr;
   if (IS_BACKDOOR(vAddr)) {
     return vAddr;
   }
    mAddr = (MA)Em_QC64Reload(vAddr,QC64_READ);
    if (mAddr) return MEMADDR_TO_K0(M_FROM_CPU(cpuNum),mAddr);
   return 0;
}


/* This function acesses true TLB state */
void qc_mmu_switch( int cpuNum, unsigned old_asid, unsigned new_asid,
                    uint forceSelfSwitch)
{
  int numTlbEntries;
  int i;
  EmbraState *P = EMP + cpuNum;

  /* Optimizations - Dont cxt switch to self (that is solid) */
  if( old_asid == new_asid )
	return;

  quick_ASID[cpuNum] = new_asid;

  numTlbEntries = P->numTlbEntries;
  for(i = 0; i < numTlbEntries; i++ ) {
     /* If the entry is (1)valid, (2)has the previous asid, and (3)does */
     /* not have the global bit set, then invalidate that page in the */
     /* quick check array */
     int global = IS_GLOBAL_HI( P->tlbEntry[i].Hi);
     if( GET_ASID( P->tlbEntry[i].Hi ) == old_asid && !global) {
        if( embra.emode == EMBRA_CACHE ) {
           qc_cache_inval_page( cpuNum, i);
        }
        qc_tlb_inval_page( cpuNum, i);
     }
  }
  /*  QC64Check(P, new_asid); */
}


void qc_CheckForDuplicate(CPUState *P,  int index)
{
   int j;
   Reg hi = P->tlbEntry[index].Hi & ~TLBHI_G;
   if (IS_UNMAPPED_TLBHI(hi)) return;
   for(j=0;j<P->numTlbEntries;j++) {
      Reg other = P->tlbEntry[j].Hi & ~TLBHI_G;
      if (j==index) continue;
      if (IS_UNMAPPED_TLBHI(other) || (other == 0)) continue;
      if (other==(hi&~TLBHI_G)) {
         CPUWarning("Duplicate tlb entry: new=0x%llx old=0x%llx indx=%d\n", 
                    (Reg64)hi, (Reg64)other, j);
      }
   }
}

void qc_CheckForDuplicates(CPUState *P)
{
   Reg hiEntries[MAX_NTLBENTRIES];
   int i,j;
   for(i = 0; i < P->numTlbEntries; i++ ) {
      Reg hi = P->tlbEntry[i].Hi;
      hiEntries[i] = hi & ~TLBHI_G;
      if (IS_UNMAPPED_TLBHI(hi)) continue;
      for(j=0;j<i;j++) {
         ASSERT( hiEntries[j] != hi);
      }
   }
}


void EmFirewallChange(PA pAddr, uint grant, uint64 cpumask)
{
   MA mAddr = PHYS_TO_MEMADDR(M_FROM_CPU(EMP->myNum),pAddr);
   VA vAddr = PHYS_TO_K0(pAddr);
   uint cpu;

   ASSERT(embra.emode == EMBRA_PAGE);   /* this function doesn't support
                                         * cache mode yet 
                                         */
   if (grant) {
      /* easy case: only need to update kseg0 that might be denied.
       * kseg2 and kuseg will get added on next qc miss 
       */
      for (cpu = 0; cpu < TOTAL_CPUS; cpu++) {
         if ( ! (cpumask & (1 << cpu)))
            continue;
         if (!TCcoherence_is_code(PHYS_TO_MEMADDR(M_FROM_CPU(cpu), pAddr))) {
           RemoveAddrQC64(EMP+cpu,vAddr);
         }
      }

   } else {
      for (cpu = 0; cpu < TOTAL_CPUS; cpu++) {
         if ( ! (cpumask & (1 << cpu)))
            continue;

         /* Denying access that used to be granted.  Take it out of kseg0...
          */
         RemoveAddrQC64(EMP+cpu, vAddr);         

      }
   }
}

/****************************************************************************/
/* phys_mem_ref wrapper */
/* This implements the "fast reload" from the physically indexed quick */
/* check array pQC */ 
/***********************************************************************/
/* Returning 0 means rewind QC, returning a value means use that value */

MA phys_mem_ref(VA vAddr, EmVQCMemState new_state, MA mAddr, int cpuNum)

{
   PLN pline;
   phys_info_t pLineInfo;
   PA pAddr;
   EmbraState* P = &EMP[cpuNum];
   MA retval;
   /* ASSERT( cpuNum < NUM_CPUS );*/

   if( VQC_INST( new_state ) ) {
      K0A k0Addr;
      vAddr = IN_BD( vAddr )?CLEAR_BD( vAddr ) + INST_SIZE: vAddr;
      k0Addr = non_excepting_tv(cpuNum, vAddr);    /* MMU lookup */
      if( k0Addr ) {
         pAddr = K0_TO_PHYS_REMAP(k0Addr, cpuNum);
      } else {
         /* TLB fault */
         retval =  mem_ref( vAddr, new_state, cpuNum );
         ASSERT( !retval || (uint)retval >0x1000);
         return retval;
      }
   } else {
      if( (uint)mAddr < 0x1000 ) {
         /* TLB fault */
         retval= mem_ref( vAddr, new_state, cpuNum );
         ASSERT( !retval || (uint)retval >0x1000);
         return retval;
      }
      pAddr = MEMADDR_TO_PHYS(  M_FROM_CPU(P->myNum),mAddr );
   }

   /* VQC missed */
   /* STAT_VQC(new_state);*/


   pline = ADDR2SLINE(pAddr);

   pLineInfo = P->qc_p[pline];


   switch( new_state ) {
   case MEM_INVALID:
      ASSERT(0);
      break;
   case MEM_I_EXCLUSIVE:
      ASSERT(0);
      break;
   case MEM_D_EXCLUSIVE:
      /* Expensive Assert */
      /* ASSERT( P->qc_v[ADDR2SLINE(vAddr)] == MEM_INVALID || 
         VQC_SHARED( P->qc_v[ADDR2SLINE(vAddr)] ) );     */

      if( PQC_DIRTY( pLineInfo ) &&
          ( PQC_VLINE( pLineInfo ) == ADDR2SLINE( vAddr ) ||
            !PQC_VLINE( pLineInfo ) )
          /* The problem is that the kernel can write a location, then */
          /* NOT set the dirty bit for the TLB entry which allows user */
          /* to write to this location */
          /* Returns 1 for K0 addresses */
          && Em_Is_Tlb_Writable(cpuNum, vAddr, CURRENT_ASID(cpuNum) ) ) {
         /* VASSERT( cache_verify_excl(cpuNum, pline), 
            ("%d vAddr 0x%x pAddr 0x%x state %d", 
            cpuNum, vAddr, pAddr, new_state) );  EXP
            */
         set_qc_state(cpuNum, ADDR2SLINE(vAddr), pline, new_state );
         /* Use below line to support parallel cache mode */
         /* return (MPinUP || NUM_CPUS == 1) ? PHYS_TO_MEMADDR( pAddr ): 0;*/
         retval = PHYS_TO_MEMADDR(M_FROM_CPU(P->myNum), pAddr );
         ASSERT( !retval || (uint)retval >0x1000);
         return retval;

      }

    
      break;
   case MEM_I_SHARED:
   case MEM_D_SHARED:
      if (new_state == MEM_I_SHARED) { 
         VASSERT( (vAddr == CLEAR_BD(P->PC) || vAddr == CLEAR_BD(P->PC)+INST_SIZE),
                  ("vAddr 0x%x\nPC 0x%x\n",
                   vAddr, P->PC) );
      }
      /* Either the line is invalid and we are reading */
      /* or the line is exclusive and we are executing.  I need to */
      /* see that case to detect self-modified code */
      /* Expensive Assert */
      /* VASSERT( ( (P->qc_v[ADDR2SLINE(vAddr)] == MEM_INVALID) ||
         (VQC_INST(new_state) &&
         (VQC_EXCL(P->qc_v[ADDR2SLINE(vAddr)])) ) ),
         ("%d vAddr 0x%x QC_V 0x%x\n", 
         cpuNum, vAddr, P->qc_v[ADDR2SLINE(vAddr)]) ); */
     
      if( PQC_VALID( pLineInfo ) &&
          ( PQC_VLINE( pLineInfo ) == ADDR2SLINE( vAddr ) ||
            !PQC_VLINE( pLineInfo ) ) &&
          /* The problem is that the kernel can read/write a */
          /* location, then */ 
          /* NOT set the valid bit for the TLB entry which allows user */
          /* access to this location */
          /* Returns 1 for K0 addresses */
       
          Em_Is_Tlb_Readable(cpuNum, vAddr,CURRENT_ASID(cpuNum) ) ) {
  
         /* If we are detecting an execute after write hazard, this */
         /* downgrades the line to read/exec so that future writes */
         /* will be detected */
         /* Otherwise this condition is detected in mem_ref */
         /* VASSERT( cache_verify_shared(cpuNum, pline), 
            ("%d vAddr 0x%x pAddr 0x%x state %d", 
            cpuNum, vAddr, pAddr, new_state) ); EXP */

         set_qc_state(cpuNum, ADDR2SLINE(vAddr), pline, new_state );

         /* Use below line to support parallel cache mode */
         /* return (MPinUP || NUM_CPUS == 1) ? PHYS_TO_MEMADDR( pAddr ) : 0; */

         retval= PHYS_TO_MEMADDR(M_FROM_CPU(cpuNum), pAddr );
         ASSERT( !retval || (uint)retval >0x1000);
         return retval;
      }
      break;
   }
   /* Can't just filter backdoor addresses because some of them are relocated */
   /* Returning a non-zero result causes the quick check to not rewind */
   /* No need to rewind when we are MPinUP */
   retval= mem_ref( vAddr, new_state, cpuNum );
   ASSERT( !retval || (uint)retval >0x1000);
   return retval;
}



/**********************************************************************
 * PhysArray Memory Reference :
 *   called on a miss in the MMU or (hit in MMU and miss in PhysArray)
 **********************************************************************/

unsigned pa_mem_ref(VA vAddr, EmVQCMemState new_state, MA mAddr, int cpuNum)
{


#if SIMBASEADDR != 0x78000000
   /* Dispatch backdoor references quickly */
   if( IS_BACKDOOR(vAddr) ) {
      STAT_INC( backdoor_ref );
      STAT_INC( backdoor_unaltered_ref );
      return vAddr;
   }
#endif


   return (unsigned) mem_ref(vAddr, new_state, cpuNum);
}


static void QC64Check(EmbraState *P, int myASID)
{
    int i, idx;
    for (i = 0; i < QC64_NUM_ENTRIES; i++) {
       if (P->kernelMMU[i].vpn != QC64_INVALID_VPN) {
          VA va = P->kernelMMU[i].vpn * DEFAULT_PAGESZ;
          if (IS_UNMAPPED_ADDR(va)) continue;
          idx = Tlb_Lookup( P->myNum, GET_REGION(va), GET_VPN2(va), myASID );
          if (idx > 0) { 
             int szEntry; 
             Reg lo_reg;
             PA pAddr;
             idx--;
             szEntry = P->tlbEntrySize[idx];
             /* Which lo register? */
             if (va & (TlbEntrySz[szEntry].offset_mask+1))
                lo_reg = P->tlbEntry[idx].Lo1;
             else
                lo_reg = P->tlbEntry[idx].Lo0;
             ASSERT(IS_VALID(lo_reg));
             if (P->kernelMMU[i].writable) { 
                ASSERT(IS_DIRTY(lo_reg));
             }
             /*
               pAddr = ((((GET_PFN(lo_reg)))*DEFAULT_PAGESZ) & 
               ~(VA)TlbEntrySz[szEntry].offset_mask) + 
               (va & TlbEntrySz[szEntry].offset_mask);
               ASSERT(pAddr == ((uint)P->kernelMMU[i].ma)-MEMADDRBASE); */

             ASSERT((P->QC64TLBBackMap[idx] & TlbEntrySz[szEntry].vpn_mask) == ((va/DEFAULT_PAGESZ) & TlbEntrySz[szEntry].vpn_mask));
          } else ASSERT(0);
       }
    }
          
}


/****************************************************************************/
/* Debugging functions.  They verify invariants */
/****************************************************************************/
/* Insure qc maps what the TLB wants mapped */
void qc_consistency_check( int cpuNum )
{
}


#endif