ms_param.h
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/*
* Copyright (C) 1996-1998 by the Board of Trustees
* of Leland Stanford Junior University.
*
* This file is part of the SimOS distribution.
* See LICENSE file for terms of the license.
*
*/
/*
* param_ss1pl - Parameters file for superscalar model 1,
* with precise interrupts.
*
* This models a superscalar processor with a short pipeline.
* Cache accesses are single cycle, and FP operations take
* generally 2 to 3 cycles.
*
* Jim Bennett
* 1993, 1994, 1995
*/
#ifndef MS_PARAM_H
#define MS_PARAM_H
/*
* Number and types of registers in the CPU
*/
#define N_IREG 34 /* Number of integer registers */
#define N_FREG 32 /* Number of floating point registers */
/* (in single precision) */
#define FPREG N_IREG /* Offset to FP registers */
#define HILOREG (N_IREG+N_FREG) /* Offset to HI and LO registers */
#define FPCTL (HILOREG+2) /* Offset to FP control registers */
#define TOT_REG (FPCTL+2) /* Total number of 32-bit registers */
#define SP 29 /* Index of stack pointer in reg file */
#define LP 31 /* Index of link pointer in reg file */
#define CNDREG 32 /* FP condition register. */
/*
* Reorder buffer size (TOTAL_INST), instruction window size,
* load/store buffer size, and the nature of the instruction
* reordering.
*/
#define TOTAL_INST 64 /* Reorder buffer size */
#define IWIN_SIZE 64 /* Instruction window size */
#define LOAD_BYPASS 1 /* Bypass values from stores to loads */
#define PRECISE 1 /* Support precise interrupts */
#define LDST_BUFFER_SIZE 32 /* Load/store buffer size */
#define LDST_BUFFER_MASK 0x1f /* Mask for circular increment */
/*
* Bandwidth parameters
*/
#define FETCH_WIDTH 4 /* Max fetches per cycle */
#define ISSUE_WIDTH 4 /* Max issues per cycle */
#define CACHE_WIDTH 2 /* Max loads+stores per cycle */
#define WBACK_WIDTH 4 /* Max register writes per cycle */
#define GRAD_WIDTH 4 /* Max graduations per cycle */
#define THREAD_WIDTH 5 /* Max number of threads to follow - Supports
* up to four predicted branch and one active one. */
#define MAX_ACT_THREADS 1 /* (during speculative execution) */
/*
* Branch prediction parameters
*/
#define BP_TABLE_SIZE 1024
#define BP_RETURN_STACK 32
#define BRANCH_LIKELY 1 /* Support branch likely instructions */
/*
* Latencies of the various operations of the functional units
*/
#ifdef ONE_PHASE_LS
#define PC_LATENCY 2 /* Latency of primary data cache access */
#else
#define PC_LATENCY 1
#endif
#define BRANCH_SLOTS 1 /* Number of branch delay slots */
#define BRANCH_LATENCY 1 /* Latency of branch instructions */
#define TAKEN_LATENCY 1 /* Latency for taken branch prediction */
#define FALLTHRU_LATENCY 1 /* Latency for fall-thru branch pred. */
#define MULT_LATENCY 5 /* Latency of integer multiply */
#define DIV_LATENCY 34 /* Latency of integer divide */
#define FPADD_LATENCY 2 /* Latency of FP add and subtract */
#define FPMULS_LATENCY 3 /* Latency of single precision multiply */
#define FPMULD_LATENCY 3 /* Latency of double precision multiply */
#define FPDIVS_LATENCY 12 /* Latency of single precision divide */
#define FPDIVD_LATENCY 12 /* Latency of double precision divide */
#define FPSQRTS_LATENCY 35 /* Single precision square root */
#define FPSQRTD_LATENCY 35 /* Double precision square root */
#define FPABS_LATENCY 1 /* Absolute value */
#define FPNEG_LATENCY 1 /* Negation */
#define FPCVT_LATENCY 2 /* Latency of floating point convert */
#define FPCVTSW_LATENCY 2 /* Latency of convert to fixed point */
#define FPCVTDW_LATENCY 2 /* Latency of convert to fixed point */
#define FPCMP_LATENCY 2 /* Latency of floating point compare */
#endif /* MS_PARAM_H */