ms_simos.c
3.83 KB
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
/*
* Copyright (C) 1996-1998 by the Board of Trustees
* of Leland Stanford Junior University.
*
* This file is part of the SimOS distribution.
* See LICENSE file for terms of the license.
*
*/
#include "ms.h"
#include "memref.h"
#include "cpu_state.h"
#include "simmisc.h"
#include "remap.h"
#include "machine_params.h"
/*******************************************************************
* Interface routines to R4000 simos
* Basem A. Nayfeh
******************************************************************/
bool
InterruptIsPending(struct s_cpu_state *st)
{
CPUState *P = (CPUState *) (st->mipsyPtr);
P->CP0[C0_CAUSE] = ((P->CP0[C0_CAUSE] & ~CAUSE_EXTINTBITS) |
((P->intrBitsPtr[0] << CAUSE_IPSHIFT) & CAUSE_EXTINTBITS));
if (((P->CP0[C0_CAUSE] & P->CP0[C0_SR]) & SR_IMASK)
&& (P->CP0[C0_SR] & SR_IEC)
&& !(P->CP0[C0_SR] & (SR_EXL|SR_ERL))) {
return TRUE;
}
return FALSE;
}
Result
ReadICache(int cpuNum, VA vAddr, PA pAddr, Inst *pInst)
{
return MemRefReadInst(cpuNum,vAddr,pAddr,pInst);
}
#define HOST_DATA_ADDR(vAddr, paddr, cpu) \
(PHYS_TO_MEMADDR(M_FROM_CPU(cpu),paddr)+(IS_REMAPPED_PADDR(paddr,cpu) ? remapVec->NodeAddr[cpu] : 0))
Result
DCacheFetchShared(int cpuNum, VA vAddr, PA pAddr, int flags, char **dataPtr)
{
(*dataPtr) = (char *)HOST_DATA_ADDR(vAddr, pAddr, cpuNum);
return SUCCESS;
}
Result
DCacheFetchExclusive(int cpuNum, VA vAddr, PA pAddr, int size, char **dataPtr)
{
/* This is bogus as is because we don't handle an SC failure */
/* See below for the old interface */
(*dataPtr) = (char *)HOST_DATA_ADDR(vAddr, pAddr, cpuNum);
return SUCCESS;
}
#if 0
Result
DCacheFetchShared(int cpuNum, VA vAddr, PA pAddr, int flags,
char **dataPtr) {
int mhtind;
Result ret;
MemRefHandle handle;
int accessType;
int MXSAction;
if (flags & MXS_SECOND_TIME) {
goto DCFSHit;
}
accessType = MEMREF_ACCESS_READ|MEMREF_SOURCE_DFETCH;
if (flags & LL_FLAVOR) {
accessType |= MEMREF_FLAVOR_LL;
}
handle = MemRef(cpuNum, accessType, vAddr, pAddr);
if (handle != MEMREF_NOSTALL) {
/* BAN: Just point the dataPtr to the handle which serves as a unique */
/* id in place of the MHT index. This will be used when calling */
/* back into MXS using DoMxsAction along with the contents of */
/* MXSAction */
(*dataPtr) = (char *) handle;
MXSAction = GetMxsAction(PE[cpuNum].st);
#ifdef VERBOSE_TRACE
CPUPrint("M P: %2d\tA: %8x\tH: %8x\n",cpuNum,pAddr,handle);
#endif
return STALL;
}
DCFSHit:
(*dataPtr) = (char *)DATA_STORAGE(vAddr, pAddr, cpuNum);
return SUCCESS;
}
Result
DCacheFetchExclusive(int cpuNum, VA vAddr, PA pAddr, int size,
char **dataPtr) {
int mhtind;
Result ret;
MemRefHandle handle;
int accessType;
int MXSAction;
if (size & MXS_SECOND_TIME) {
goto DCFEHit;
}
accessType = MEMREF_ACCESS_WRITE;
if (size & SC_FLAVOR) {
accessType |= MEMREF_FLAVOR_SC;
}
handle = MemRef(cpuNum, accessType, vAddr, pAddr);
if (handle != MEMREF_NOSTALL) {
/* BAN: First special case the SC */
if (size & SC_FLAVOR) {
(*dataPtr) = NULL;
return SCFAILURE;
}
/* BAN: Just point the dataPtr to the handle which serves as a unique */
/* id in place of the MHT index. This will be used when calling */
/* back into MXS using DoMxsAction along with the contents of */
/* MXSAction */
(*dataPtr) = (char *) handle;
MXSAction = GetMxsAction(PE[cpuNum].st);
#ifdef VERBOSE_TRACE
CPUPrint("M P: %2d\tA: %8x\tH: %8x\n",cpuNum,pAddr,handle);
#endif
return STALL;
}
DCFEHit:
(*dataPtr) = (char *)DATA_STORAGE(vAddr, pAddr, cpuNum);
return SUCCESS;
}
#endif /*0*/